link to page 8 ADCMP609Data SheetMINIMUM INPUT SLEW RATE REQUIREMENT comparators. With additional capacitive loading or poor bypassing, With the rated load capacitance and normal good PCB design oscillation may be encountered. These oscillations are due to the practice (as discussed in the Optimizing Performance section), high gain bandwidth of the comparator in combination with these comparators should be stable at any input slew rate with feedback through parasitics in the package and PCB. In many no hysteresis. Broadband noise from the input stage is observed applications, chatter is not harmful. in place of the violent chatter seen with most other high speed Rev. C | Page 10 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATIONS CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
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