Datasheet ADN2891 (Analog Devices) - 10

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ADN2891 Data Sheet THEORY OF OPERATION LIMITING AMPLIFIER LOSS OF SIGNAL (LOS) DETECTOR Input Buffer
The on-chip LOS circuit drives LOS to logic high when the The ADN2891 limiting amplifier provides differential inputs input signal level falls below a user-programmable threshold. (PIN/NIN), each having single-ended, on-chip, 50 Ω termina- The threshold level can be set to anywhere from 3.5 mV p-p to tion. The amplifier can accept either dc-coupled or ac-coupled 35 mV p-p, typical, and is set by a resistor connected between signals; however, an ac-coupled signal is recommended. Using a the THRADJ pin and VEE. See Figure 8 and Figure 9 for the dc-coupled signal, the amplifier needs a correct input common- LOS threshold vs. THRADJ. The ADN2891 LOS circuit has an mode voltage and enough headroom to handle the dynamic electrical hysteresis greater than 2.5 dB to prevent chatter at the input signal strength. Additional y, TIA output offset drifts may LOS signal. The LOS output is an open-col ector output that degrade receiver performance. must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor. The ADN2891 limiting amplifier is a high gain device. It is
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
susceptible to dc offsets in the signal path. The pulse width The ADN2891 has an on-chip, RSSI circuit. By monitoring the distortion presented in the NRZ data or a distortion generated current supplied to the photodiode, the RSSI circuit provides an by the TIA may appear as dc offset or a corrupted signal to the accurate, average power measurement. The output of the RSSI is ADN2891 inputs. An internal offset correction loop can a current that is directly proportional to the average amount of compensate for certain levels of offset. To compensate for more PIN photodiode current. Placing a resistor between the offset, an external capacitor connected between the CAZ1 and RSSI_OUT pin and GND converts the current to a GND CAZ2 pins maybe necessary. For GbE and FC applications, no referenced voltage. This function eliminates the need for external capacitor is necessary; however, for SONET appli- external RSSI circuitry for SFF-8472-compliant optical cations, a 0.01 µF capacitor helps the input signal offset receivers. For more information, see Figure 14 to Figure 18. compensation and provides a 3 dB cutoff frequency at 1 kHz.
SQUELCH MODE CML Output Buffer
Driving the SQUELCH input to logic high disables the limiting The ADN2891 provides differential CML outputs, OUTP and amplifier outputs. Using LOS output to drive the SQUELCH OUTN. Each output has an internal 50 Ω termination to VCC. input, the limiting amplifier outputs stop toggling anytime a signal input level to the limiting amplifier drops below the programmed LOS threshold. The SQUELCH pin has a 100 kΩ, internal, pul -down resistor. Rev. B | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS PCB DESIGN GUIDELINES Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP OUTLINE DIMENSIONS ORDERING GUIDE