link to page 1 link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 6 link to page 6 link to page 6 link to page 7 link to page 8 link to page 19 link to page 19 link to page 19 link to page 20 link to page 20 link to page 20 link to page 21 link to page 21 link to page 21 link to page 22 link to page 22 link to page 23 link to page 24 link to page 25 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 27 link to page 27 link to page 27 link to page 27 link to page 27 link to page 28 link to page 29 link to page 29 ADRF6520Data SheetTABLE OF CONTENTS Features .. 1 Distortion Characteristics ... 22 Applications ... 1 Maximizing the Dynamic Range ... 22 Functional Block Diagram .. 1 Key Parameters for Quadrature-Based Receivers .. 23 General Description ... 1 SPI Register and Timing .. 24 Revision History ... 2 Register Read/Write Timing ... 25 Specifications ... 3 Applications Information .. 26 Absolute Maximum Ratings .. 6 Basic Connections .. 26 Thermal Resistance .. 6 Supply Decoupling ... 26 ESD Caution .. 6 Input Signal Path .. 26 Pin Configuration and Function Descriptions ... 7 Output Signal Path ... 26 Typical Performance Characteristics ... 8 DC Offset Compensation Loop Enabled .. 26 Theory of Operation .. 19 Serial Port Connections ... 26 Input VGAs ... 19 Enable/Disable Function ... 27 RMS Detector .. 19 Gain Pin Decoupling ... 27 Programmable Filters ... 20 RMS Detector Connections .. 27 Variable Gain Amplifiers ... 20 VGA2 Gain step response ... 27 Output Buffers/ADC Drivers ... 20 Linear Operation of the ADRF6520 .. 27 DC Offset Compensation Loop .. 21 Evaluation Board .. 28 Programming the ADRF6520 ... 21 Outline Dimensions ... 29 Noise Characteristics ... 21 Ordering Guide .. 29 REVISION HISTORY 4/2017—Revision 0: Initial Version Rev. 0 | Page 2 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
