Datasheet AD537 (Analog Devices) - 7

AD537 SYNCHRONOUS OPERATION
The SYNC terminal at pin 2 of the DIP package can be used to
LOGIC AD537 GND OUTPUT RECOVERED
synchronize a free running AD537 to a master oscillator, either
1 14 FREQUENCY 3.9V SIGNAL
at a multiple or a sub-multiple of the primary frequency. The
+V DEC/ S +15V 2 DRIVER 13 SYN
preferred connection is shown in Figure 10. The diodes are used
14 3 12 1 12
to produce the proper drive magnitude from high level signals.
CURR CAP FREQ 10k -TO- 0.01µF CONTROL 4 BUF 11 2 11 COM-
The SYNC terminal can also be used to shut off the oscillator.
INPUT FREQ POSITE 0 TO –10V CONV ERROR
Shorting the terminal to +V
5 10 SIGNAL 6
S will stop the oscillator, and the
SIGNAL VOS INPUT
±
1V PK
output will go high (output NPN off).
10 VTEMP 6 9 PRECISION
±
12V PK V 7 8 T VOLTAGE –VS VREF 7 REFERENCE 8 V –15V R AD537 1 14 fOUT
Figure 12. Linear Phase-Locked Loop
CS R VSYNC 2 13 +V DRIVER S
Noise on the input signal affects the loop operation only slightly;
1000pF 3 12
it appears as noise in the timing current, but this is averaged out
CURR- CT BUF
by the timing capacitor. On the other hand, if the input fre-
4 TO-FREQ 11 CONV
quency changes there is a net error voltage at Pin 5 which acts
VIN 5 10
to bring the oscillator back into quadrature. Thus, the output at
NOTE: IF V 6 9 SYNC >2V p-p VT PRECISION
Pin 14 is a noise-free square-wave having exactly the same fre-
USE THIS LIMITER C VOLTAGE S 7 VR REFERENCE 8
quency as the input signal. The effectiveness of this circuit can
V 2 SYNC 10k
be judged from Figure 13 which shows the response to an input
1N4148
of 1 V rms 1 kHz sinusoid plus 1 V rms Gaussian noise. The positive supply to the AD537 is reduced by about 4 V in order to keep the voltages at Pins 11 and 12 within the common-mode Figure 10. Connection for Synchronous Operation range of the AD534. Figure 11 shows the maximum pull-in range available at a given Since this is also a first-order loop the circuit possesses a very signal level; the optimum signal is a 0.8 to 1.0 volt square wave; wide capture range. However, even better noise-integrating signals below 0.1 volt will have no effect; signals above 2 volts properties can be achieved by adding a filter between the multi- p-p will disable the oscillator. The AD537 can normally be syn- plier output and the VCO input. Details of suitable filter charac- chronized to a signal which forces it to a higher frequency up to teristics can be found in the standard texts on the subject. 30% above the nominal free-running frequency, it can only be brought down about 1–2%.
1V RMS SIGNAL +1V RMS NOISE 30% FREQUENCY LOCK-IN 20% RANGE 10% OUTPUT 0.2 0.4 0.6 0.8 1.0 VSYNC SQUARE-WAVE INPUT VOLTS p-p
Figure 13. Performance of AD537 Linear Phase Locked Figure 11. Maximum Frequency Lock-ln Range vs. Loop Sync Signal By connecting the multiplier output to the lower end of the tim-
LINEAR PHASE LOCKED LOOP
ing resistor and moving the control input to Pin 5, a high resis- The phase-locked-loop F/V circuit described earlier operates tance frequency-control input is made available. However, due from an essentially noise-free binary input. PLL’s are also used to the reduced supply voltage, this input cannot exceed +6 V. to extract frequency information from a noisy analog signal. To
TRANSDUCER INTERFACE
do this, the digital phase-comparator must be replaced by a lin- The AD537 was specifically designed to accept a broad range of ear multiplier. In the implementation shown in Figure 12, the input signals, particularly small voltage signals, which may be triangular waveform appearing across the timing capacitor is converted directly (unlike many V-F converters which require used as one of the multiplier inputs; the signal provides the signal preconditioning). The 1.00 V stable reference output is other input. It can be shown that the mean value of the multi- also useful in interfacing situations, and the high input resis- plier output is zero when the two signals are in quadrature. In tance allows nonloading interfacing from a source of varying this condition, the ripple in the error signal is also quite small. resistance, such as the slider of a potentiometer. Thus, the voltage at Pin 5 is essentially zero, and the frequency is determined primarily by the current in the timing resistor, controlled either manually or by a control voltage. REV. C –7–