Datasheet FL7921R (ON Semiconductor) - 9

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FL7921R ELECTRICAL CHARACTERISTICS
(VDD = 15 V and TA = −40~105C, unless otherwise noted) (continued)
Symbol Parameter Conditions Min Typ Max Unit PWM Output Section
tR PWM Gate Output Rising Time CL = 3 nF, VDD = 12 V, − 80 110 ns 20~80% tF PWM Gate Output Falling Time CL = 3 nF, VDD = 12 V, − 40 70 ns 20~80%
Current Sense Section
tPD Delay to Output − 150 200 ns VLIMIT Limit Voltage on CSPWM Pin for Over−Power IDET < 75 mA, TA = 25C 0.85 0.875 0.90 V Compensation IDET = 185 mA, TA = 25C 0.72 0.75 0.78 IDET = 350 mA, TA = 25C 0.55 0.59 0.63 VSLOPE Slope Compensation (Note 4) tON = 45 ms, 0.25 0.30 0.35 V RANGE = Open tON = 0 ms 0.05 0.10 0.15 tON−BNK Leading−Edge Blanking Time − 300 ns VCS−FLOATING CSPWM Pin Floating VCSPWM Clamped High CSPWM Pin Floating 4.5 − 5.0 V Voltage VCS−OV CSPWM Pin Open Protection (Note 4) − 3 − V tCS−H Delay with CSPWM Pin Floating CSPWM Pin Floating 100 150 200 ms
RT Pin Over−Temperature Protection Section
TOTP Internal Threshold Temperature for OTP (Note 4) 125 140 155 C TOTP−HYST Hysteresis Temperature for Internal OTP (Note 4) − 30 − C IRT Internal Source Current of RT Pin 90 100 110 mA VRT−REC Auto Recovery−Mode Triggering Voltage 0.75 0.80 0.85 V VRT−RE−REC Auto Recovery−Mode Release Voltage VRT−REC VRT−REC VRT−REC V +0.15 +0.20 +0.25 VRT−OTP−LEVEL Threshold Voltage for Two−level Debounce Time 0.45 0.50 0.55 V tRT−OTP−H Debounce Time for OTP − 10 − ms tRT−OTP−L Debounce Time for Externally Triggering VRT < VRT−OTP−LEVEL, 70 115 160 ms TA = 25C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Guaranteed by design.
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