Datasheet TEA1501 (NXP) - 8

Philips Semiconductors TEA1501 GreenChip SMPS controller IC 7.3.8 Gate driver
The gate driver switches the power switch. The power switch is turned on at the beginning of every oscillator cycle and is turned off by the primary current comparator or by the maximum on-time. The power switch is also prevented from turning on if VAUX has reached its regulation level or in the case of active overtemperature protection or active undervoltage lockout protection.
7.3.9 Power switch
The power switch is an integrated high voltage Lateral Diffused Metal Oxide Semiconductor Transistor (LDMOST) with a Rdson of 40 Ω, a maximum peak drain voltage of 650 V, a maximum continuous drain voltage of 500 V and a maximum drain current of 0.25 A.
7.3.10 Primary current comparator
The primary current comparator senses the voltage across the external sense resistor RSOURCE which reflects the primary current. The detection level of the comparator is 0.5 V. The power switch is switched off quickly when the source voltage exceeds this detection level. The comparator has a typical propagation delay of 80 ns. If the dV/dt of the drain voltage has to be limited for ElectroMagnetic Interference (EMI) reasons, a capacitor can be connected between the DRAIN and SOURCE pins of the TEA1501. The discharge current of this EMI capacitor does not flow through the sense resistor RSOURCE and does not activate the comparator.
7.3.11 Leading edge blanking
To prevent the power switch from switching off due to the discharge current of the capacitance on the DRAIN pin a Leading Edge Blanking (LEB) circuit has been implemented. The leading edge blanking time is defined as the maximum duration time needed to discharge the capacitance at the drain of the power switch. The leading edge blanking time is determined by the reference resistor to obtain an accurate and temperature independent time. The LEB time tracks with the period time of the switch oscillator.
7.3.12 Modulator
The modulator determines the regulation level of VAUX. For a burst duty cycle from 0 % to 40 % the AUX voltage is regulated to 20 V. For stable operation in Burst mode a decrease in regulation voltage is integrated for a burst duty cycle above 40 %. At 100 % burst duty cycle the regulation voltage is 17.5 V. TEA1501_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 31 March 2006 8 of 21
Document Outline 1. General description 2. Features 2.1 Distinctive features 2.2 Green features 2.3 Protection features 3. Quick reference data 4. Ordering information 5. Block diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 7.1 System operation 7.1.1 On/off 7.1.2 Start-up 7.1.3 Operation 7.1.4 Data transfer 7.2 Waveforms in the Off mode, Start-up mode and Operation mode 7.3 Circuit block description 7.3.1 On/off/data section 7.3.2 VAUX management 7.3.3 Start-up current source 7.3.4 Reference block 7.3.5 Temperature protection 7.3.6 Switch oscillator 7.3.7 Burst oscillator 7.3.8 Gate driver 7.3.9 Power switch 7.3.10 Primary current comparator 7.3.11 Leading edge blanking 7.3.12 Modulator 7.3.13 Counter 7.3.14 Supply current tracking 7.4 Design Equations 7.4.1 Primary peak current 7.4.1.1 Minimum value of RSOURCE 7.4.2 Switch oscillator 7.4.2.1 Range of RREF values 7.4.3 Leading edge blanking 7.4.4 Burst oscillator 7.4.4.1 Minimum value of CBURST 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Test information 11.1 Quality information 12. Package outline 13. Soldering 13.1 Introduction to soldering surface mount packages 13.2 Reflow soldering 13.3 Wave soldering 13.4 Manual soldering 13.5 Package related soldering information 14. Revision history 15. Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks 16. Contact information 17. Contents