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PIN CONFIGURATIONIN GND GND GND GND DRV DD SET GND OUT SW SW SW V OUT P P P P PHASE GL V V V A SCLK SDA SALRT RT_SYNC V V 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 51 51 30 SW V OUT 52 52 29 SW VOUT 53 53 62 28 SW VOUT P 54 54 GND 27 SW VOUT 55 55 26 SW VOUT 61 56 56 25 SW A V GND OUT 57 57 24 SW VOUT 63 58 58 23 SW VOUT V IN 59 59 22 SW VOUT 60 60 21 SW VOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IN IN IN SW SW SW V V CIN V GH V EN OT GND NC OUT OUT A SEN+ SEN- GOOD V V BO ADDR V V PHASE PHASE P
Fig. 2 - Pin Configuration - Transparent View PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION1 to 3, 48 to 60 SW Switch node 4, 5, 8, 47, 63 VIN Input voltage for power stage 6, 7, 42 PHASE Phase node, return of high side gate driver 9 GH High side gate signal for test purpose 10 VCIN Input to the internal 5 V LDO. Connect this pin to VIN on PCB 11 EN Enable pin. Active high 12 BOOT Bootstrap voltage for high side gate driver 13 ADDR PMBus address configuration pin 14, 37, 61 AGND Analog ground 15 PGOOD Power good pin with open drain connection 16 VSEN+ Positive input for output remote sense 17 NC Leave this pin not connected 18 VSEN- Negative input for output remote sense 19 to 32 VOUT Output voltage terminals Clock synchronization pin. Frequency can be set by connecting a resistor to A 33 RT_SYNC GND. Pending on master / salve configuration, a clock can be send / receive via the pin 34 SALRT PMBus alert. Connect to external host interface if desired 35 SDA PMBus data. Connect to external host interface 36 SCLK PMBus clock. Connect to external host interface 38 VSET Output voltage set point by connecting a resistor from VSET to AGND 39 VDD Internal 5 V circuits supply voltage. VDD is a LDO output, connect a 1 μF decoupling capacitor to AGND Supply voltage for internal gate drive. V 40 V DRV is a LDO output. Connect a 4.7 μF decoupling capacitor DRV to PGND 41 GL Low side MOSFET gate monitor 43 to 46, 62 PGND Power ground. Common return for internal MOSFETs S23-0736-Rev. C, 12-Sep-2023
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