1 Ω , Low-Voltage, Single-SupplySPDT Analog SwitchesTest Circuits/Timing Diagrams (continued) V+ MAX4625 V LOGIC INH V+ INPUT VINL NC VNC V V COM NC NO V 0.8 • V NO OUT R R L L CL CL 50 50 Ω Ω 35pF 35pF 0.8 • VOUT LOGIC GND INPUT VNQ tMBB CL INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 3b. Make-Before-Break Interval (MAX4625 only) MAX4624/MAX4625 V+ ∆VOUT MAX4624 MAX4625 V+ VOUT RGEN NC COM VOUT OR NO IN C OFF OFF L V ON GEN GND IN ON OFF OFF IN VINL TO VINH Q = (∆VOUT)(CL) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 4. Charge Injection +5V 10nF V OFF-ISOLATION = 20log OUT V NETWORK IN ANALYZER V+ 50Ω 50Ω VOUT 0V OR V+ IN VIN ON-LOSS = 20log COM V IN MAX4624 VOUT NC CROSSTALK = 20log MAX4625 V IN VOUT MEAS REF NO 50Ω GND 50Ω 50Ω MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. Figure 5. On-Loss, Off-Isolation, and Crosstalk 8_______________________________________________________________________________________
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