Datasheet CA3080, CA3080A (Intersil) - 3

CA3080, CA3080A
Electrical Specifications
For Equipment Design, VSUPPLY = 15V, Unless Otherwise Specified
(Continued) CA3080 CA3080A PARAMETER TEST CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS
Peak Output Positive IABC = 5A, RL =  25 - 13.8 - 12 13.8 - V Voltage Negative 25 - -14.5 - -12 -14.5 - V Positive IABC = 500A, RL =  25 12 13.5 - 12 13.5 - V Negative 25 -12 -14.4 - -12 -14.4 - V Amplifier Supply Current IABC = 500A 25 0.8 1 1.2 0.8 1 1.2 mA Device Dissipation IABC = 500A 25 24 30 36 24 30 36 mW IABC = 0, VTP = 0 25 - 0.08 - - 0.08 5 nA Magnitude of Leakage Current IABC = 0, VTP = 36V 25 - 0.3 - - 0.3 5 nA Propagation Delay IABC = 500A 25 - 45 - - 45 - ns Common-Mode Rejection Ratio IABC = 500A 25 80 110 - 80 110 - dB Open-Loop Bandwidth IABC = 500A 25 - 2 - - 2 - MHz Slew Rate Uncompensated 25 - 75 - - 75 - V/s Compensated 25 - 50 - - 50 - V/s
Schematic Diagram 7 V+ D3 Q D 4 3 D2 Q6 Q7 Q5 D4 Q9 Q8 INVERTING OUTPUT INPUT 2 Q1 Q2 NON- 6 INVERTING 3 INPUT Q10 AMPLIFIER 5 Q3 Q11 BIAS INPUT V- D1 D6 4 Typical Applications V+ = 15V VS =

15V 0.01

F 62k 7 10k 5 LOAD 3 + (SCOPE PROBE) 390pF 51 CA3080, A 6 OUTPUT 300 1V/DIV. 5pF 2 - 1M 4 0.01

F 10k V- = -15V INPUT 5V/DIV. 0.001

F TIME (0.1

s/DIV.) FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3080 AND CA3080A IN A UNITY-GAIN VOLTAGE FOLLOWER CONFIGURATION AND ASSOCIATED WAVEFORM
FN475 Rev.6.00 Page 3 of 11 Jan 13, 2017