link to page 12 link to page 12 link to page 31 link to page 31 link to page 12 link to page 31 link to page 12 PMG1-S1 Datasheet PMG1-S1 has three distinct mechanisms to detect the reverse ■ Mechanism 3: A comparator senses the 20% voltage of the current as shown in Figure 5. CSN pin and compares it against Vref = 1.15 V for 5-V provider VBUS application. This comparator signals an RCP event ■ Mechanism 1: A comparator senses the voltage drop across whenever CSN voltage goes above Vbus_max_det voltage external Rsense through pins CSP and CSN. This comparator given in Table 33 for a 5-V application. The output of this signals an RCP event whenever CSN > CSP by the Vcsa_rcp comparator RCP3 is shown in Figure 5. Note that Vref is voltage given in Table 33. The output of this comparator RCP1 programmable and the voltage divider has an option to use is shown in Figure 5. 10% or 20% value. For a higher voltage of the provider, the ■ Mechanism 2: A comparator senses the voltage drop across VBUS device automatically adjusts this threshold. provider FET through CSN and VBUS pin of PMG1-S1. This When any one of the three comparator outputs show an RCP comparator signals an RCP event whenever VBUS > CSN by event, then the provider FET is turned OFF. The firmware has an the Vcomp_rcp voltage given in Table 33. The output of this option to enable or disable the individual mechanism depending comparator RCP2 is shown in Figure 5. on the application. Figure 5. RCP Mechanism Vcsa_rcp Vcomp_rcp VBUS_P VBUS to Type-C Connector Provider Side Regulator VBUS_C CSP VBUS_P_CTRL CSN VBUS RCP2 RCP1 RCP Detect Comparator RCP Detect (DC.RCP.45) (DC.RCP.44) RCP3 Vref Vbux_max_det PMG1-S1 (DC.RCP.46) CSA The inputs to the UV comparator are a division (10% or 20%) of PMG1-S1 chip has an integrated high-side current sense VBUS supply voltage and a reference voltage. The reference amplifier that is capable of detecting current in the order of 100 voltage is configurable in the range (200 mV to 2190 mV) in mA across a 5-mΩ external resistor in the provider path. This is steps of 10 mV. used to monitor the current load and detect system faults such Overcurrent Protection on VBUS as OCP and SCP while sourcing VBUS to the Sink on the Type C port so that the PD controller can shut down the Provider FET PMG1-S1 integrates a high-side current sense amplifier to to protect devices. detect overcurrent on the VBUS. The VBUS load is sensed using an external 5-m sense resistor connected between the “CSP” Slew-Rate Controllable Gate Driver and “CSN” pins and compared against the OCP detector PMG1-S1 has a programmable slew-rate controllable Gate threshold. The OCP detector threshold is programmable and Driver, which can help in limiting the in-rush currents during controlled by the firmware. connect events. True Random Number Generator Overvoltage and Undervoltage Protection on VBUS PMG1-S1 supports a True Random Number Generator (TRNG) PMG1-S1 implements an undervoltage/overvoltage (UVOV) to generate random numbers. These random numbers can be detection circuit for the VBUS supply. The threshold for OV and used to generate random challenges as part of the initiator UV detection can be set independently. Both UV and OV implementation of the USB Type C Authentication Specification detectors have programmable thresholds and are controlled by (USBTCAS). the firmware. The inputs to the OV comparator are a division (8% or 10%) of VBUS supply voltage and a reference voltage. The reference voltage is configurable in the range (200 mV to 2190 mV) in steps of 10 mV. Document Number: 002-31597 Rev. *B Page 11 of 40 Document Outline PMG1-S1 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S1 General Description Features USB-PD Type-C Legacy Charging (source and sink) Mux Integrated VBUS Load Switch Controller LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC USB 2.0 Mux VBUS Discharge VBUS Regulator Gate Driver for VBUS PFET on Consumer Path Charger Detect High-Voltage Tolerant CC Lines VBUS Load Switch Controller for Provider Path RCP CSA Slew-Rate Controllable Gate Driver Overvoltage and Undervoltage Protection on VBUS Overcurrent Protection on VBUS True Random Number Generator CPU and Memory Subsystem CPU Flash SROM SRAM Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Power System Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect VSYS Switch CSA VBUS UV/OV Consumer Side PFET Gate Driver Provider Side PFET Gate Driver Provider Side PFET RCP DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
