Datasheet PMN50XP (NXP) - 6

NXP Semiconductors PMN50XP P-channel TrenchMOS extremely low level FET
03ar95 001aae334 -1.2 −10−3 V I GS(th) D max (V) (A) -0.8 typ −10−4 min typ max min -0.4 −10−5 0 −10−6 -60 0 60 120 180 0 −0.2 −0.4 −0.6 −0.8 −1.0 Tj (°C) VGS (V) I = í0.25 m A; V = V T = 25 °C; V = í5 V D DS GS j DS
Fig 5. Gate-source threshold voltage as a function of Fig 6. Sub-threshold drain current as a function of junction temperature gate-source voltage
03aq05 03aq10 150 2 V -2 R GS (V) = DSon a (mΩ) 120 1.5 -2.5 90 -3 1 -3.5 60 -4.5 0.5 30 0 0 0 -5 -10 -15 -20 -60 0 60 120 180 I T D (A) j (°C) T = 25 °C R j DSon a = RDSon(25°C)
Fig 7. Drain-source on-state resistance as a function Fig 8. Normalized drain-source on-state resistance of drain current; typical values factor as a function of junction temperature
PMN50XP_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 October 2007 6 of 11
Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents