STGAP2SICS Datasheet Galvanically isolated 4 A single gate driver for SiC MOSFETs Features • High voltage rail up to 1200 V • Driver current capability: 4 A sink/source @25°C • dV/dt transient immunity ±100 V/ns in full temperature range • Overall input-output propagation delay: 75 ns • Separate sink and source option for easy gate driving configuration • 4 A Miller CLAMP dedicated pin option • UVLO function • Gate driving voltage up to 26 V • 3.3 V, 5 V TTL/CMOS inputs with hysteresis • Temperature shut-down protection • Standby function • 6 kV galvanic isolation • Wide body SO-8W package Description The STGAP2SICS is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two Product status link different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The STGAP2SICS configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations Product label provide high flexibility and bill of material reduction for external components. The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption. DS13402 - Rev 1 - September 2020 www.st.com For further information contact your local STMicroelectronics sales office. Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and “safe state” 6.3 Control inputs 6.4 Miller Clamp function 6.5 Watchdog 6.6 Thermal shutdown protection 6.7 Standby function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-8W package information 10.2 SO-8W suggested land pattern 11 Ordering information Revision history Contents List of tables List of figures
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