ISOSD61 Datasheet 16-Bit isolated Σ-∆ modulator, single-ended and LVDS interfaces Features • Up to 25 MHz external clock input for easier synchronization • ±320 mV full scale analog input range • 16-bit resolution, no missing codes • 13-bit typical ENOB • 86 dB typical SNR • -83 dB typical THD • ±3 LSB typical INL • ±1 % maximum Gain Error • Low Voltage Differential Signaling (LVDS) and Single - ended (TTL/CMOS) options • –40°C to +125°C extended industrial temperature range • SO-16 wide package • 30 kV/µs typical High Common-mode transient immunity • 6000 VPEAK Isolation Voltage VIOTM • 1200 VPEAK Working Voltage VIORM Application Current and voltage sensing in: • Industrial motor control • Solar inverter Product status link • UPS ISOSD61 • Electric vehicle charger Product label • Factory automation • Telecom and server power supply Description The ISOSD61 is a galvanic isolated second order Sigma-Delta modulator based on embedded transformer coupling technology. It converts an analog input signal with maximum range of ±320mV into a high speed, 25 Msps, 1-bit digital data stream. The signal information can be rebuilt by means of a digital filtering. The modulator is isolated from the digital I/O section through a high-speed isolated data coupling, whose performances are far better than other isolated transceivers like optocouplers. DS13605 - Rev 3 - March 2021 www.st.com For further information contact your local STMicroelectronics sales office. Document Outline Cover image Product status link / summary Features Application Description 1 Device overview 2 Pin description 3 Device specifications 4 Terminology 5 Theory of operation 6 Package description 7 Ordering information Revision history Contents List of tables List of figures
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