Datasheet A17700 (Allegro) - 4

Pressure Sensor Interface and Signal Conditioning IC A17700 with Polynomial Signal Compensation and Advanced Diagnostics PINOUT DIAGRAMS AND TERMINAL LIST
NC NC NC NC NC NC 24 23 22 21 20 19 NC 1 18 NC NC 2 17 VCC NC 3 16 NC PAD NC 4 15 GND TEST1 5 14 OUT TEST2 6 13 NC 7 8 9 10 11 12 VP VN VBRG VBRG_2 VBRGGND VBRGGND_2
Package ES, 24-Pin QFN Pinout Diagram Terminal List Table Number Name Function
1 to 4 NC No internal connection [1] 5 TEST1 Factory Test Pin 1; connect to GND 6 TEST2 Factory Test Pin 2; connect to GND 7 VBRGGND_2 2nd GND pin for the bridge [2] 8 VP Positive bridge output 9 VBRG_2 2nd bridge supply pin [3] 10 VBRGGND GND pin for the bridge 11 VN Negative bridge output 12 VBRG Bridge supply 13 NC No internal connection [1] 14 OUT Analog / open drain output 15 GND Ground 16 NC No internal connection [1] 17 VCC Supply voltage 18 to 24 NC No internal connection [1] – PAD Exposed thermal pad [1] For increased ESD performance, connect NC (no connection) pins to GND. [2] This is a second ground pin for the bridge intended for single layer PCB design. Internally connected to VBRGGND. Connect to GND if not used. [3] This is a second bridge supply pin intended for single layer PCB design. Internally connected to VBRG. Leave floating if not used. 4 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Functional Block Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Operating Characteristics Functional Description Bandwidth Selection Output Response Time Power-On Time Front End Gain Adjustment Front End Differential Offset Adjustment Input Signal Range Calculation Fine Adjustment and Temperature Compensation Output Protocols Digital Output Mode Selection Digital Output Driver Fall Time Selection Broken Wire Detection Diagnostic Features Programming: Manchester Communication Entering Manchester Coding Manchester Interface Message Structure CRC Device Access Shadow Registers Device EEPROM and Register Access Lock EEPROM Map Volatile Registers Map Power Derating Package Outline Drawing