link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 ADPA7001CHIPSData SheetPIN CONFIGURATION AND FUNCTION DESCRIPTIONS234567AA121A2A343A4ADDDDDDDDGGVVGGVVVV8RFOUTADPA7001CHIPS1 RFIN12B1B2B34B3B4BFTGGDDDDGGDDDDREDEVVVVVVVV 002 161514 131211 10 9 16895- Figure 2. Pad Configuration Table 6. Pad Function Descriptions Pad No.MnemonicDescription 1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2 VGG12A Gate Control Pad for the First and Second Stage Amplifiers. See Figure 4 for the interface schematic. 3, 4 VDD1A, Drain Bias Voltage Pads for the First and Second Stage Amplifiers. External bypass capacitors of 100 pF, 0.1 μF, and VDD2A 4.7 μF are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic. 5 VGG34A Gate Control Pad for the Third and Fourth Stage Amplifiers. See Figure 4 for the interface schematic. 6, 7 VDD3A, Drain Bias Voltage Pads for the Third and Fourth Stage Amplifiers. External bypass capacitors of 100 pF, 0.1 μF, and VDD4A 4.7 μF are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic. 8 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic. 9 VDET DC Voltage Representing the RF Output Power. This pad is rectified by the diode that is biased through an external resistor. See Figure 9 for the interface schematic. 10 VREF DC Voltage of the Diode. This pad is biased through an external detector circuit used for temperature compensation of VDET. See Figure 10 for the interface schematic. 11, 12 VDD4B, Drain Bias Voltage Pads for the Fourth and Third Stage Alternative Bias Configuration. External bypass VDD3B capacitors of 100 pF, 0.1 μF, and 4.7 μF are required. See Figure 7 for the interface schematic. 13 VGG34B Gate Control Pad for the Third and Fourth Stage Alternative Bias Configuration. Coupling capacitors are required. See Figure 8 for the interface schematic. 14, 15 VDD2B, Drain Bias Voltage Pads for the Second and First Stage Alternative Bias Configuration. External bypass VDD1B capacitors of 100 pF, 0.1 μF, and 4.7 μF are required. See Figure 7 for the interface schematic. 16 VGG12B Gate Control Pad for the First and Second Stage Alternative Bias Configuration. Coupling capacitors are required. See Figure 8 for the interface schematic. Die Bottom GND Ground. Die bottom must be connected to RF/dc ground. See Figure 6 for the interface schematic. Rev. B | Page 6 of 18 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS 50 GHz TO 70 GHz FREQUENCY RANGE 70 GHz TO 90 GHz FREQUENCY RANGE 90 GHz TO 95 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE
