2ED24427N01F10 A dual-channel low-side gate driver ICFigure 6Bridge Tied Gate Driver waveforms The waveforms in Figure 6 show that: The lower LLK is, the lower and shorter is the ringing on the Fets gate voltage, particular care must be paid to guarantee that the max Vgs voltage of the Fet is not exceeded during operation. The lower LLK is, the shorter the propagation delay is from the driver to the gate of the Fet and the higher the peak current is into its gate. The higher Lm is, the lower ILM is; at the primary side the gate peak current, summed to ILM, constitute the total current flowing out of the gate driver. Datasheet 10 of 21 V 2.0 www.infineon.com/gdLowSide 2019-11-10
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