PE43610UltraCMOS® RF Digital Step Attenuator (reference state). But a logic LOW on the LE pin ensure that the pins LE, SDI/D1, CLK/D2, A0/D4, A1/ during the power up, the part should default to D5, and A2/D6 are set to logic LOW. maximum attenuation state. If the DSA powers up in either latched or direct Dynamic operation between serial and paral el paral el mode, the pins LE, SDI/D1, CLK/D2, A0/D4, programming modes is not supported. A1/D5, and A2/D6 must be set to logic LOW and the If the DSA powers up in serial mode (P/S = HIGH), pin SDO/D3 set to high impedance prior to toggling to prior to toggling to paral el mode, the user must serial addressable mode (P/S = HIGH). Table 7 • Summary of Power-up Functionality of the PE43610ModeP/SLE During Power-upD[6:1] Pin StatusDSA State at Power-up 1 0 Maximum at enuation Serial mode 1 1 Reference state 1 Floating Maximum at enuation 0 0 Don’t care Maximum at enuation Latch paral el mode 0 Floating Don’t care Maximum at enuation Attenuation state depends Data present on the D[6:1] lines upon the logic present on the Direct paral el mode 0 1 pins D[6:1] D[6:1] lines floating 28 dB at enuation state Figure 3 • Serial Addressable Timing Diagram A[2:0] X P/S X TCLK TSISU TSIH TCLKH TCLKL LE TLEPW TLESU CLK TSDOPD D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] SDI X 0 0 0 0 0 0 0 D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] SDO 0 0 0 0 0 0 0 Notes: 1. SPI mode 0: - SDI data is captured on the CLK’s rising edge - SDO data is valid on CLK falling edge 2. CLK shared pin with 1 dB parallel control bit D2 3. SDI shared pin with 0.5 dB parallel control bit D1 4. SDO shared pin with 2 dB parallel control bit D3 5. A0 shared pin with 4 dB parallel control bit D4 6. A1 shared pin with 8 dB parallel control bit D5 7. A2 shared pin with 16 dB parallel control bit D6 8. Serial data bits D[7], D[0], and A[7:3] must be set to logic low 9. X = Undefined Page 8 of 21 DOC-93588-3 – (06/2020) www.psemi.com Document Outline Features Applications Product Description Optional External VSS Control Absolute Maximum Ratings ESD Precautions Latch-up Immunity Recommended Operating Conditions Electrical Specifications Switching Frequency Spur-free Performance Glitch-safe Attenuation State The PE43610 features a novel architecture to provide safe transition behavior when changing attenuation states. When RF input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing c... Truth Tables Serial Addressable Register Map Programming Options Parallel/Serial Selection Parallel Mode Interface For direct parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values changes the device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface Power-up Control Settings Typical Performance Data Pin Configuration Packaging Information Moisture Sensitivity Level Package Drawing Top-Marking Specification Tape and Reel Specification Ordering Information
