Datasheet ADP7102 (Analog Devices) - 3

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Data Sheet ADP7102 SPECIFICATIONS
VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 3.3 20 V OPERATING SUPPLY CURRENT IGND IOUT = 100 μA, VIN = 10 V 400 μA IOUT = 100 μA, VIN = 10 V, TJ = −40°C to +125°C 900 μA IOUT = 10 mA, VIN = 10 V 450 μA IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 1050 μA IOUT = 150 mA, VIN = 10 V 650 μA IOUT = 150 mA, VIN = 10 V, TJ = −40°C to +125°C 1250 μA IOUT = 300 mA, VIN = 10 V 750 μA IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 1400 μA SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 12 V 40 μA EN = GND, VIN = 12 V, TJ = −40°C to +125°C 75 μA INPUT REVERSE CURRENT IREV-INPUT EN = GND, VIN = 0 V, VOUT = 20 V 0.3 μA EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to +125°C 5 μA OUTPUT VOLTAGE ACCURACY Fixed Output Voltage VOUT IOUT = 10 mA −0.8 +0.8 % Accuracy 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, −2 +1 % TJ = −40°C to +125°C Adjustable Output Voltage VADJ IOUT = 10 mA 1.21 1.22 1.23 V Accuracy 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, 1.196 1.232 V TJ = −40°C to +125°C LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −0.015 +0.015 %/V LOAD REGULATION1 ∆VOUT/∆IOUT IOUT = 1 mA to 300 mA 0.2 %/A IOUT = 1 mA to 300 mA, TJ = −40°C to +125°C 1.0 %/A ADJ INPUT BIAS CURRENT ADJI-BIAS 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, 10 nA ADJ connected to VOUT SENSE INPUT BIAS CURRENT SENSEI-BIAS 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, 1 μA SENSE connected to VOUT, VOUT = 1.5 V DROPOUT VOLTAGE2 VDROPOUT IOUT = 10 mA 20 mV IOUT = 10 mA, TJ = −40°C to +125°C 40 mV IOUT = 150 mA 100 mV IOUT = 150 mA, TJ = −40°C to +125°C 175 mV IOUT = 300 mA 200 mV IOUT = 300 mA, TJ = −40°C to +125°C 325 mV START-UP TIME3 tSTART-UP VOUT = 5 V 800 μs CURRENT-LIMIT THRESHOLD4 ILIMIT 450 575 750 mA PG OUTPUT LOGIC LEVEL PG Output Logic High PGHIGH IOH < 1 μA 1.0 V PG Output Logic Low PGLOW IOL < 2 mA 0.4 V PG OUTPUT THRESHOLD Output Voltage Falling PGFALL −9.2 % Output Voltage Rising PGRISE −6.5 % Rev. E | Page 3 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA Thermal Resistance ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PROGRAMABLE UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FEATURE NOISE REDUCTION OF THE ADJUSTABLE ADP7102 CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE