Datasheet ADCMP565 (Analog Devices) - 8

link to page 8 link to page 8 ADCMP565 TIMING INFORMATION
LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL VIN VREF ± VOS INPUT VOLTAGE VOD tPDL tPLOH Q OUTPUT 50% t t F PDH 50% Q OUTPUT tPLOL tR
02820-0-003 Figure 3. System Timing Diagram The timing diagram in Figure 3 shows the ADCMP565 compare
Symbol Timing Description
and latch features. Table 4 describes the terms in the diagram. tH Minimum Minimum time after the negative hold time transition of the Latch Enable
Table 4. Timing Descriptions
signal that the input signal must
Symbol Timing Description
remain unchanged to be acquired and held at the outputs tPDH Input to output Propagation delay measured from high delay the time the input signal crosses tPL Minimum Minimum time that the Latch the reference (± the input offset latch enable Enable signal must be high to voltage) to the 50% point of an pulse width acquire an input signal change output low-to-high transition tS Minimum Minimum time before the t setup time negative transition of the Latch PDL Input to output Propagation delay measured from low delay the time the input signal crosses Enable signal that an input signal the reference (± the input offset change must be present to be voltage) to the 50% point of an acquired and held at the outputs output high-to-low transition tR Output rise Amount of time required to t time transition from a low to a high PLOH Latch enable Propagation delay measured from to output high the 50% point of the Latch Enable output as measured at the 20% delay signal low-to-high transition to and 80% points the 50% point of an output low- tF Output fall Amount of time required to to-high transition time transition from a high to a low t output as measured at the 20% PLOL Latch enable Propagation delay measured from to output low the 50% point of the Latch Enable and 80% points delay signal low-to-high transition to VOD Voltage Difference between the the 50% point of an output high- overdrive differential input and reference to-low transition input voltages Rev. 0 | Page 8 of 16 Document Outline SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING INFORMATION APPLICATION INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE