link to page 21 link to page 21 link to page 67 link to page 63 link to page 65 DS28E18 1-Wire® to I2C/SPI Bridge with Command Sequencer Note 16: Time from VIO = 80% of VPUP and VIO = 20% of VPUP at the negative edge on IO at the beginning of the presence detect pulse. Note 17: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a device present. The power-up presence detect pulse could be outside this interval, but will be complete within 2ms after power-up. Note 18: ε in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 19: δ in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 20: ISPU is the current drawn from IO during a strong pullup (SPU) operation. The pullup circuit on IO during the SPU operation should be such that the voltage at IO is greater than or equal to VSPUMIN. A low-impedance bypass of RPUP activated during the SPU operation is the recommended method to meet this requirement. See the Typical Application Circuits for details. Note 21: All I2C timing values are referred to VIH(MIN) and VIL(MAX) levels. Note 22: See Figure 10 for I2C timing symbol details. Rise and fall times are system dependent and not included. Note 23: The DS28E18 provides 2.5μs (standard mode), 675ns (fast mode), or 280ns (Fm+) minimum hold time, not including rise/fall time, for the SDA signal. Note 24: CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007). Note 25: See Figure 12 for SPI timing symbol details. The fMCK options listed only effect speed for the SPI WRITE/READ BYTE command. The fMCK for the SPI WRITE/READ BIT command is variable up to a maximum of 134kHz. Rise and fall times are system dependent and not included. 19-100832 www.maximintegrated.com Maxim Integrated | 8 Document Outline General Description Applications Benefits and Features Simplified Application Block Diagram Absolute Maximum Ratings Package Information 8 TDFN-EP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Pin Configuration DS28E18 Pin Description Functional Diagram Block Diagram Detailed Description 64-Bit ROM ID Power-Up ROM ID Serialization 1-Wire Bus System Hardware Configuration Transaction Sequence Initialization 1-Wire ROM Function Commands Search ROM [F0h] Read ROM [33h] Match ROM [55h] Skip ROM [CCh] Resume [A5h] Overdrive-Skip ROM [3Ch] Overdrive-Match ROM [69h] 1-Wire Signaling and Timing Read/Write Time Slots Master-to-Slave Slave-to-Master Improved Network Behavior Device Function Commands Command Start (66h) Write Sequencer Command (11h) Read Sequencer Command (22h) Run Sequencer Command (33h) Device Configuration and Status Commands Write Configuration Command (55h) Read Configuration Command (6Ah) Write GPIO Configuration (83h) Read GPIO Configuration (7Ch) Device Status Command (7Ah) Sequencer Commands I2C Sequencer Interface Commands I2C Start Command I2C Stop Command I2C Write Data Command I2C Read Data Command I2C Read Data with NACK End Command SPI Sequencer Commands SPI Write/Read Byte(s) Command SPI Write/Read Bit(s) Command SS_HIGH Command SS_LOW Command Sequencer Utility Commands GPIO_CTRL Write Command GPIO_CTRL Read Command GPIO_BUF Write Command GPIO_BUF Read Command Delay Command SENS_VDD On Command SENS_VDD Off Command I2C Overview I2C Definitions Bus Idle or Not Busy START Condition STOP Condition Repeated START Condition Data Valid SPI Overview SPI Timing SPI Timing Diagram Power-Up of GPIO/I2C Pins Timeout Typical Application Circuits DS28E18 Configured as an I2C Master Typical Application Circuits (continued) DS28E18 Configured as an SPI Master Ordering Information Revision History
