Datasheet ADN8834 (Analog Devices) - 7

Data Sheet ADN8834 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 D T1 NDL MPG G N2P N1P N1N I I I OU T P A PGNDL PGNDL OUT1 IN1P IN2P 24 23 22 21 20 19 IN2N 1 18 PGNDL OUT2 2 17 LDR ADN8834 VLIM/SD 3 16 PVINL B VLIM/ LDR LDR IN1N IN2N TOP VIEW SD ILIM 4 15 PVINS (Not to Scale) VDD 5 14 SW VREF 6 13 PGNDS C PVIN PVIN ITEC OUT2 ILIM 2.54mm 7 8 9 10 11 12 B C ND SY/ EC SF ITE NDS AG EN VT G P NOTES
200
D SW SW VTEC EN/SY VDD 1. EXPOSED PAD. SOLDER TO THE ANALOG GROUND PLANE ON THE BOARD.
12954-
0.5mm PITCH E PGNDS PGNDS SFB AGND VREF 2.54mm ADN8834
002
TOP VIEW (BALLS ON THE BOTTOM SIDE)
12954- Figure 2. WLCSP Pin Configuration (Top View) Figure 3. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions Pin No. WLCSP LFCSP Mnemonic Description
A1, A2 18, 19 PGNDL Power Ground of the Linear TEC Controller. N/A1 20 TMPGD Temperature Good Output. A3 21 OUT1 Output of the Error Amplifier. A4 23 IN1P Noninverting Input of the Error Amplifier. A5 24 IN2P Noninverting Input of the Compensation Amplifier. B1, B2 17 LDR Output of the Linear TEC Controller. B3 22 IN1N Inverting Input of the Error Amplifier. B4 1 IN2N Inverting Input of the Compensation Amplifier. B5 3 VLIM/SD Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is pulled low, the device shuts down. C1, C2 N/A1 PVIN Power Input for the TEC Controller. N/A1 16 PVINL Power Input for the Linear TEC Driver. N/A1 15 PVINS Power Input for the PWM TEC Driver. C3 11 ITEC TEC Current Output. C4 2 OUT2 Output of the Compensation Amplifier. C5 4 ILIM Current Limit. This pin sets the TEC cooling and heating current limits. D1, D2 14 SW Switch Node Output of the PWM TEC Controller. D3 9 VTEC TEC Voltage Output. D4 8 EN/SY Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input can be applied to this pin. D5 5 VDD Power for the Controller Circuits. E1, E2 12, 13 PGNDS Power Ground of the PWM TEC Controller. E3 10 SFB Feedback of the PWM TEC Controller Output. E4 7 AGND Signal Ground. E5 6 VREF 2.5 V Reference Output. N/A1 0 EPAD Exposed Pad. Solder to the analog ground plane on the board. 1 N/A means not applicable. Rev. B | Page 7 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide