link to page 1 link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 8 link to page 10 link to page 10 link to page 15 link to page 15 link to page 15 link to page 15 link to page 16 link to page 20 link to page 20 link to page 25 link to page 29 link to page 33 link to page 33 link to page 33 link to page 33 link to page 33 link to page 34 link to page 34 link to page 34 link to page 35 link to page 35 link to page 35 link to page 35 link to page 35 link to page 36 link to page 36 link to page 36 AD9361Data SheetTABLE OF CONTENTS Features .. 1 Theory of Operation .. 33 Applications ... 1 General... 33 Functional Block Diagram .. 1 Receiver.. 33 General Description ... 1 Transmitter .. 33 Revision History ... 2 Clock Input Options .. 33 Specifications ... 3 Synthesizers ... 34 Current Consumption—VDD_Interface .. 8 Digital Data Interface... 34 Current Consumption—VDDD1P3_DIG and VDDAx Enable State Machine ... 34 (Combination of all 1.3 V Supplies) ... 10 SPI Interface .. 35 Absolute Maximum Ratings ... 15 Control Pins .. 35 Reflow Profile .. 15 GPO Pins (GPO_3 to GPO_0) ... 35 Thermal Resistance .. 15 Auxiliary Converters .. 35 ESD Caution .. 15 Powering the AD9361 .. 35 Pin Configuration and Function Descriptions ... 16 Packaging and Ordering Information ... 36 Typical Performance Characteristics ... 20 Outline Dimensions ... 36 800 MHz Frequency Band ... 20 Ordering Guide .. 36 2.4 GHz Frequency Band .. 25 5.5 GHz Frequency Band .. 29 REVISION HISTORY 11/2016—Rev. E to Rev. F11/2013—Rev. C to Rev. D Changes to Features Section and General Description Section . 1 Changes to Ordering Guide .. 36 Change to Transmitter—General, Center Frequency Parameter, Minimum Column, Table 1 ... 4 9/2013—Revision C: Initial Version11/2014—Rev. D to Rev. E Changes to Table 1 .. 7 Rev. F | Page 2 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
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