link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 4 link to page 4 link to page 5 link to page 7 link to page 8 link to page 9 link to page 9 link to page 9 link to page 10 link to page 12 link to page 17 link to page 17 link to page 17 link to page 18 link to page 18 link to page 18 link to page 19 link to page 20 link to page 22 link to page 22 link to page 23 link to page 24 link to page 24 link to page 25 link to page 25 link to page 26 link to page 26 link to page 27 link to page 27 link to page 27 link to page 28 link to page 28 link to page 28 link to page 29 link to page 30 link to page 30 link to page 30 link to page 31 link to page 32 link to page 32 link to page 32 link to page 33 link to page 36 link to page 36 link to page 37 link to page 38 link to page 38 link to page 38 link to page 38 link to page 39 link to page 40 link to page 40 link to page 41 link to page 42 link to page 42 AD7294-2Data SheetTABLE OF CONTENTS Features .. 1 Command Register .. 26 Applications ... 1 ADC Result Register .. 26 General Description ... 1 TSENSE1 and TSENSE2 Result Registers ... 27 Revision History ... 2 TSENSEINT Result Register .. 27 Functional Block Diagram .. 3 DACA, DACB, DACC, and DACD Value Registers ... 27 Specifications ... 4 Alert Status Register A, Alert Status Register B, and Alert Status Register C ... 28 DAC Specifications... 4 Channel Sequence Register ... 28 ADC Specifications .. 5 Configuration Register .. 29 General Specifications ... 7 Power-Down Register .. 30 Timing Characteristics .. 8 DATALOW and DATAHIGH Registers .. 30 Absolute Maximum Ratings .. 9 Hysteresis Registers .. 30 Thermal Resistance .. 9 Remote Channel TSENSE1 and TSENSE2 Offset Registers ... 31 ESD Caution .. 9 I2C Interface .. 32 Pin Configuration and Function Descriptions ... 10 General I2C Timing .. 32 Typical Performance Characteristics ... 12 Serial Bus Address Byte ... 32 Terminology .. 17 Interface Protocol ... 33 DAC Terminology .. 17 Modes of Operation ... 36 ADC Terminology .. 17 Command Mode .. 36 Theory of Operation .. 18 Autocycle Mode .. 37 ADC Overview ... 18 Alerts and Limits Theory .. 38 ADC Transfer Functions ... 18 ALERT_FLAG Bit ... 38 Analog Inputs .. 19 Alert Status Registers ... 38 Current Sensor .. 20 DATALOW and DATAHIGH Monitoring Features .. 38 Analog Comparator Loop ... 22 Hysteresis ... 39 Temperature Sensor ... 22 Applications Information .. 40 DAC Operation ... 23 Base Station Power Amplifier Monitor and Control ... 40 ADC and DAC Reference .. 24 Gain Control of Power Amplifier ... 41 VDRIVE Feature .. 24 Outline Dimensions ... 42 Register Settings .. 25 Ordering Guide .. 42 Address Pointer Register ... 25 REVISION HISTORY 6/13—Revision 0: Initial Version Rev. 0 | Page 2 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide
