Product Brief AVR-DA (Microchip) - 9

AVR-DA Pinout 2.3 48-Pin VQFN and TQFP
(EXTCLK) I 4 3 2 1 0 D D D 6 (RESET) 5 4 3 A A A A A N D P F F F F P P P P P G V U P P P P 4 3 2 1 0 9 8 7 45 46 47 48 4 4 4 4 4 3 3 3 PA5 1 36 PF2 PA6 2 35 PF1 (XTAL32K2) PA7 3 34 PF0 (XTAL32K1) PB0 4 33 PE3 PB1 5 32 PE2 PB2 6 31 PE1 PB3 7 30 PE0 PB4 8 29 GND PB5 9 28 AVDD PC0 10 27 PD7 PC1 11 26 PD6 PC2 12 25 PD5 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 3 D D 4 5 6 7 0 1 2 3 4 C D N C C C C D D D D D P V P P P P P P P P G P
Power Special functions
Input supply Programming, debug Ground Clock, crystal PIN connected to VDD power domain PIN connected to AVDD power domain
Note:
For the AVR-DA family, the VDD and AVDD are internally connected together (no separate power domains). © 2020 Microchip Technology Inc.
Product Brief
DS40002164A-page 9 Document Outline Introduction Features AVR-DA Family Overview 1. Memory Overview 2. Peripheral Overview Table of Contents 1. Block Diagram 2. Pinout 2.1. 28-Pin SPDIP, SSOP and SOIC 2.2. 32-Pin VQFN and TQFP 2.3. 48-Pin VQFN and TQFP 2.4. 64-Pin VQFN and TQFP 3. I/O Multiplexing and Considerations 3.1. I/O Multiplexing The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service