Datasheet MAX9021, MAX9022, MAX9024 (Maxim) - 6

Micropower, Ultra-Small, Single/Dual/Quad, Single-Supply Comparators
VDD R1 VDD VDD VDD R2 IN+ IN+ VIN VREF OUT OUT 10kΩ IN- IN- VIN MAX9021 MAX9021 0.1µF VSS VSS Figure 1. Additional Hysteresis Figure 2. Time Averaging of the Input Signal for Data Recovery 2) The hysteresis band will be:
Board Layout and Bypassing
V Use 100nF bypass as a starting point. Minimize signal HYS = VTH - VTL = VDD(R2 / (R1 + R2)) trace lengths to reduce stray capacitance. Minimize the 3) In this example, let VDD = 5V and VREF = 2.5V. capacitive coupling between IN- and OUT. For slow- moving input signals (rise time > 1ms), use a 1nF VTH = 2.5V + 2.5V(R2 / (R1 + R2)) capacitor between IN+ and IN-. and
Biasing for Data Recovery
VTL = 2.5V[(1 - (R2 / (R1 + R2))] Digital data is often embedded into a bandwidth and amplitude-limited analog path. Recovering the data can 4) Select R2. In this example, we will choose 1kΩ. be difficult. Figure 2 compares the input signal to a
MAX9021/MAX9022/MAX9024
5) Select VHYS. In this example, we will choose 50mV. time-averaged version of itself. This self-biases the 6) Solve for R1. threshold to the average input voltage for optimal noise margin. Even severe phase distortion is eliminated from VHYS = VDD(R2 / (R1 + R2)) the digital output signal. Be sure to choose R1 and C1 0.050V = 5(1000Ω/(R1 + 1000Ω)) V so that: where R1 ≈ 100kΩ, VTH = 2.525V, and VTL = 2.475V. fCAR >> 1 / (2πR1C1) The above-described design procedure assumes rail- where fCAR is the fundamental carrier frequency of the to-rail output swing. If the output is significantly loaded, digital data stream. the results should be corrected.
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