Datasheet 1EDN7550U (Infineon) - 5

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EiceDRIVER™ 1EDN7550 and 1EDN8550 Single-channel EiceDRIVER™ gate-drive IC with true differential inputs Functional description 3 Functional description
Although EiceDRIVER™ 1EDNx550 is a family of non-isolated gate drivers, it extends the range of possible applications into fields usually reserved for isolated drivers, thereby generating significant system cost benefits. The key to make this possible is moving from the standard ground related to a true differential input with very high common-mode rejection. The required symmetry of the input circuitry is achieved by on-chip trimming; it finally allows to deal with peak common-mode voltages of up to ± 150 V between driver reference (GND) and system ground (SGND). 1EDNx550 is not only ideally suited for any application with unwanted shifts between driver and system ground, but may also be utilized as a high-side driver within the allowed common-mode range. Besides, switches requiring a bipolar driving voltage can be operated very easily as well.
3.1 Differential input Figure 4
depicts the signal path from the controller’s PWM output to the logic gate driver signal as implemented on 1EDNx550. Controller 1EDNx550 VS Rin1 2kW 0 PWM IN+ 15pF 1kW Cp1 12 MHz Differential DVRin DVRin / k A Pulse v = 4.5 2nd order Schmitt Extender Lowpass Trigger Cp2 15pF 1kW IN- SGND Rin2 2kW GND k = (Rin [kW] + 3) / 3
Figure 4 1EDNx550 input signal path
The controller output signal, switching between controller supply VS and zero, is applied at the one leg of a differential voltage divider, while the other is connected to the controller ground SGND. The divider ratio has to be adapted to VS to allow a fixed Schmitt-Trigger threshold voltage. For VS = 3.3 V, Rin1 and Rin2 are chosen to be 33 kΩ, resulting in a static divider ratio of k = 12 at the driver inputs and 36 at the internal voltage amplifier. With VS other than 3.3 V, Rin has to fulfil the relation: Rin1 = Rin2 = 10.9 VS − 3 kΩ Amplified by a factor of 4.5, the signal is filtered by a 2nd order low-pass filter. Taking into account the RC filter in front of the amplifier, the overall input path exhibits the frequency behavior of a 3rd order low-pass filter with a corner frequency around 12 MHz. The suppression of high frequencies is important for two reasons. Firstly, common-mode ringing, being in the 100 MHz and above range for fast-switching power systems, can effectively be damped. In addition, the high-frequency symmetry of the voltage divider is influenced by parasitic capacitances, particularly Cp1 and Cp2, the parallel capacitances of Rin1 and Rin2. They are typically in the 50 to 100 fF range, rather independent of resistor size. Without filtering, any asymmetry would translate high- frequency common-mode into differential signals. The filtered signal is then applied to a differential Schmitt-Trigger with accurate trimmed threshold levels and converted to the logic switch control signal. The subsequent pulse extender function guarantees that no pulses shorter than 25 ns are transmitted to the output, thereby further improving noise immunity. Due to the filtering requirements the input-to-output propagation delay is slightly increased to around 45 ns. By means of on-chip trimming, however, the usually more relevant propagation delay variation can still be kept low at +10 / -7 ns. Datasheet 5 Rev. 2.2 2019-12-09 Document Outline Features Description Table of contents 1 Pin configuration and description 2 Block diagram 3 Functional description 3.1 Differential input 3.1.1 Common mode input range 3.2 Driver outputs 3.3 Supply voltage and Undervoltage Lockout (UVLO) 4 Electrical characteristics and parameters 4.1 Absolute maximum ratings 4.2 Thermal characteristics 4.3 Operating range 4.4 Electrical characteristics 4.5 Timing diagram 5 Typical characteristics 6 Typical applications 6.1 Switches with Kelvin source connection (4-pin packages) 6.2 Applications with significant parasitic PCB-inductances 6.3 Switches with bipolar gate drive 6.4 High-side switches 7 Layout guidelines 8 Package information 8.1 PG-SOT23-6 package 8.2 PG-TSNP-6 package 9 Device numbers and markings Revision history Disclaimer