Datasheet PI6CG33802C (Diodes) - 10

A product Line of Diodes Incorporated
PI6CG33802C HCSL Output AC Characteristics Cont. Spec Symbol Parameters Condition Min. Typ. Max Limit Units
PCIe Gen 1(6) 20 30 86 ps(p-p) PCIe Gen 2 Low Band, 10kHz < f < 1.5MHz 0.08 0.1 3.0 ps PCIe Gen 2 High Band, 1.5MHz < f < Nyquist (50MHz) 0.99 1.3 3.1 ps PCIe Gen3 Common Clock Architecture (PLL BW of 2-4 or 2-5MHz, 0.32 0.42 1.0 ps tj Integrated Phase Jitter PHASE CDR = 10MHz) (RMS)(1,5) PCIe Gen3 Separate Reference No Spread (PLL BW of 2-4 or 2-5MHz, CDR 0.16 0.21 0.7 ps =10 MHz) PCIe Gen 4 (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz) 0.32 0.4 0.5 ps PCIe Gen 5(7) (PLL BW of 500k to 1.8MHz. CDR = 20MHz) 0.02 0.05 0.15 ps tj PCIe Gen 2, Separate Reference Inde- PH- Integrated Phase Jitter pendent Spread 0.6 0.92 2 ps SRISG2 (RMS), -0.25% Spread (PLL BW of 16MHz, CDR=5MHz) PCIe Gen 3, Separate Reference Inde- tjPH- Integrated Phase Jitter pendent Spread 0.32 0.4 0.7 ps SRISG3 (RMS), -0.25% Spread (PLL BW of 2-4MHz or 2-5MHz, CDR=10MHz) tj PCIe Gen 2, Separate Reference Inde- PH- Integrated Phase Jitter pendent Spread 0.8 1.1 2 ps SRISG2 (RMS), -0.5% Spread (PLL BW of 16MHz, CDR=5MHz) PCIe Gen 3, Separate Reference Inde- tjPH- Integrated Phase Jitter pendent Spread 0.35 0.6 0.7 ps SRISG3 (RMS), -0.5% Spread (PLL BW of 2-4MHz or 2-5MHz, CDR=10MHz)
Note:
1. Guaranteed by design and characterization—not 100% tested in production. 2. Measured from differential waveform. 3. Slew rate is measured through the Vswing voltage range centered around differential 0V, within ±150mV window. 4. It is measured using a ±75mV window centered on the average cross point. 5. See http://www.pcisig.com for complete specs. 6. Sample size of at least 100k cycles. This can be extrapolated to 108ps pk-pk @ 1M cycles for a BER of 10-12. 7. PCIe Gen 5 v0.9 specification. PI6CG33802C www.diodes.com January 2020 Document Number DS42298 Rev 3-2 10 Diodes Incorporated