STSPIN32F0601, STSPIN32F0602 600 V three-phase controller with MCU Datasheet - production dataApplications TQFP 10x10 64L pitch 0.5 Home and Industrial refrigerators compressors Industrial drives, pumps, fans Air conditioning compressors & fans Corded power tools, garden tools Home appliances Features Industrial automation Three-phase gate drivers Description – High voltage rail up to 600 V The STSPIN32F060x system-in-package is an – Driver current capability: extremely integrated solution for driving three- STSPIN32F0601: phase applications, helping designers to reduce 200/350 mA source/sink current PCB area and overall bill-of-material. STSPIN32F0602: 1/0.85 A source/sink current It embeds an STM32F031x6x7 featuring an – dV/dt transient immunity ±50 V/ns ARM® 32-bit Cortex®-M0 CPU and a 600 V triple – Gate driving voltage range from 9V to 20V half-bridge gate driver, able to drive N-channel power MOSFETs or IGBTs. 32-bit ARM® Cortex®-M0 core: – Up to 48 MHz clock frequency A comparator featuring advanced smartSD function is integrated, ensuring fast and effective – 4-Kbyte SRAM with HW parity protection against overload and overcurrent. – 32-Kbyte Flash memory with option bytes used for write/readout protection The high-voltage bootstrap diodes are also integrated, as well as anti cross-conduction, 21 general-purpose I/O ports (GPIO) deadtime and UVLO protection on both the lower 6 general-purpose timers and upper driving sections, which prevents the 12-bit ADC converter (up to 10 channels) power switches from operating in low efficiency or dangerous conditions. Matched delays between I2C, USART and SPI interfaces low and high-side sections guarantee no cycle Matched propagation delay for all channels distortion. Integrated bootstrap diodes The integrated MCU allows performing FOC, Comparator for fast over current protection 6-step sensorless and other advanced driving UVLO, Interlocking and deadtime functions algorithms including the speed control loop. Product label Smart shutdown (smartSD) function Standby mode for low power consumption On-chip debug support via SWD Extended temperature range: -40 to +125 °C September 2019 DS12981 Rev 3 1/29 This is information on a product in full production. www.st.com Document Outline 1 Block diagram Figure 1. STSPIN32F060x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F060x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F060x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history
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