MTD1N60E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off−state condition when cal- The lengths of various switching intervals (∆t) are deter- culating td(on) and is read at a voltage corresponding to the mined by how fast the FET input capacitance can be charged on−state when calculating td(off). by current from the generator. The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com- ing rise and fall because drain−gate capacitance varies plicate the analysis. The inductance of the MOSFET source greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current. the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func- t = Q/I tion of drain current, the mathematical solution is complex. G(AV) The MOSFET output capacitance also complicates the During the rise and fall time interval when switching a resis- mathematics. And finally, MOSFETs have finite internal gate tive load, VGS remains virtually constant at a level known as resistance which effectively adds to the resistance of the the plateau voltage, VSGP. Therefore, rise and fall times may driving source, but the internal resistance is difficult to mea- be approximated by the following: sure and, consequently, is not specified. tr = Q2 x RG/(VGG − VGSP) The resistive switching time variation versus gate resis- tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is where affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit RG = the gate drive resistance used to obtain the data is constructed to minimize common and Q inductance in the drain and gate circuit loops and is believed 2 and VGSP are read from the gate charge curve. readily achievable with board mounted components. Most During the turn−on and turn−off delay times, gate current is power electronic loads are inductive; the data in the figure is not constant. The simplest calculation uses appropriate val- taken with a resistive load, which approximates an optimally ues from the capacitance curves in a standard equation for snubbed inductive load. Power MOSFETs may be safely op- voltage change in an RC network. The equations are: erated into an inductive load; however, snubbing reduces td(on) = RG Ciss In [VGG/(VGG − VGSP)] switching losses. td(off) = RG Ciss In (VGG/VGSP) 500 1000 VDS = 0 V VGS = 0 V TJ = 25°C 450 VGS = 0 V T C J = 25°C iss C 400 iss 350 100 300 ANCE (pF) 250 Ciss ANCE (pF) C ACIT rss 200 ACIT Coss 10 150 C, CAP C, CAP 100 Crss Coss 50 Crss 0 1 10 5 0 5 10 15 20 25 10 100 1000 VGS VDS VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7b. High Voltage CapacitanceFigure 7a. Capacitance VariationVariation 4 Motorola TMOS Power MOSFET Transistor Device Data
