Datasheet SIC466, SiC467, SiC468, SiC469 (Vishay) - 7

SiC466, SiC467, SiC468, SiC469
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Control Scheme Power-Save Mode and Mode Pin Operation
SiC46x employs a voltage - mode COT control mechanism To improve efficiency at light-loads, SiC46x provides a set in conjunction with adaptive zero current detection which of innovative implementations to eliminate LS re-circulating allows for power saving in discontinuous conduction mode current and switching losses. The internal zero crossing (DCM). The switching frequency, fSW, is set by an external detector (ZCD) monitors SW node voltage to determine resistor Rfsw connected from fsw pin to ground. The SiC46x when inductor current starts to flow negatively. In power operates between 200 kHz to 2 MHz depending on VIN and saving mode, as soon as inductor valley current crosses VOUT conditions. zero, the device first deploys diode emulation mode by turning off the LS FET. If load further decreases, switching V R OUT = ----------------------- frequency is reduced proportional to the load condition to fsw -12 f  190  10 save switching losses while keeping output ripple within sw Note, that there is no V tolerance. IN dependency on fSW as long as VIN and VCIN are connected to the same supply. To improve the converter efficiency, the user can choose to SiC46x employs an advanced voltage - mode COT control disable the internal VDRV regulator by picking either mode 3 mechanism. or mode 4 and connecting a 5 V supply to the VDRV pin. This During steady-state operation, feedback voltage (V reduces power dissipation in the SiC46x by eliminating the FB) is compared with internal reference (0.8 V typ.) and the VDRV linear regulator losses. amplified error signal (VCOMP) is generated at the internal The mode pin supports several modes of operation as comp node. An internally generated ramp signal and VCOMP shown in table 1. An internal current source is used to set feed into a comparator. Once VRAMP crosses VCOMP, an the voltage on this pin using an external resistor: on-time pulse is generated for a fixed time. During the on-time pulse, the high side MOSFET will be turned on.
TABLE 1 - OPERATION MODES
Once the on-time pulse expires, the low side MOSFET will
POWER SAVE INTERNAL V MODE RANGE (k ) DRV
be turned on after a dead time period. The low side MOSFET
MODE REGULATOR
will stay on for a minimum duration equal to the minimum 1 0 to 100 Enabled ON off-time (tOFF_MIN.) and remains on until VRAMP crosses 2 298 to 304 Disabled ON V 3 494 to 504 Disabled OFF (1) COMP. The cycle is then repeated. 4 900 to 1100 Enabled OFF (1) Fig. 5 illustrates the operation as described above.
Note
(1) Connect a 5 V (± 5 %) supply to the VDRV pin VRAMP The mode pin is not latched to any state and can be changed on the fly. VCOMP PWM Fixed on-time
Fig. 5 - Operational Principle
S19-0911-Rev. E, 28-Oct-2019
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