Datasheet VEML6035 (Vishay) - 4

VEML6035
www.vishay.com Vishay Semiconductors
PARAMETER TIMING INFORMATION
I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
W
(SDAT) Start by ACK ACK master I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 (SDAT) ACK ACK Stop by master Data byte low Data byte high Fig. 3 - I2C Bus Timing for Sending Word Command Format I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
W
(SDAT) Start by ACK ACK master I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
R
(SDAT) Start by ACK ACK by master master I2C bus slave address byte Data byte low I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 (SDAT) NACK by Stop by master master Data byte high Fig. 4 - I2C Bus Timing for Receive Word Command Format Rev. 1.0, 12-Mar-2019
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