Datasheet AD600, AD602 (Analog Devices) - 3

link to page 32 link to page 4 link to page 32 link to page 32 link to page 32 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4
AD600/AD602 SPECIFICATIONS
Each amplifier section at TA = 25°C, VS = ±5 V, −625 mV ≤ VG ≤ +625 mV, RL = 500 Ω, and CL = 5 pF, unless otherwise noted. Specifications for the AD600/AD602 are identical, unless otherwise noted.
Table 1. AD600J/AD602J 1 AD600A/AD602A
1
Parameter Conditions Min Typ Max Min Typ Max Unit
INPUT CHARACTERISTICS Input Resistance Pin 2 to Pin 3; Pin 6 to Pin 7
98
100
102 95
100
105
Ω Input Capacitance 2 2 pF Input Noise Spectral Density2 1.4 1.4 nV/√Hz Noise Figure RS = 50 Ω, maximum gain 5.3 5.3 dB RS = 200 Ω, maximum gain 2 2 dB Common-Mode Rejection Ratio f = 100 kHz 30 30 dB OUTPUT CHARACTERISTICS −3 dB Bandwidth VOUT = 100 mV rms 35 35 MHz Slew Rate 275 275 V/μs Peak Output3 RL ≥ 500 Ω ±2.5 ±3 ±2.5 ±3 V Output Impedance f ≤ 10 MHz 2 2 Ω Output Short-Circuit Current 50 50 mA Group Delay Change vs. Gain f = 3 MHz; full gain range ±2 ±2 ns Group Delay Change vs. Frequency VG = 0 V, f = 1 MHz to 10 MHz ±2 ±2 ns Total Harmonic Distortion RL= 200 Ω, VOUT = ±1 V peak, RPD = 1 kΩ −60 −60 dBc ACCURACY AD600 Gain Error 0 dB to 3 dB gain
0
+0.5
+1 −0.5
+0.5
+1.5
dB 3 dB to 37 dB gain
−0.5
±0.2
+0.5 −1.0
±0.2
+1.0
dB 37 dB to 40 dB gain
−1
−0.5
0 −1.5
−0.5
+0.5
dB Maximum Output Offset Voltage4 VG = –625 mV to +625 mV 10
50
10
65
mV Output Offset Variation VG = –625 mV to +625 mV 10
50
10
65
mV AD602 Gain Error –10 dB to –7 dB gain
0
+0.5
+1 –0.5
+0.5
+1.5
dB –7 dB to +27 dB gain
−0.5
±0.2
+0.5 −1.0
±0.2
+1.0
dB 27 dB to 30 dB gain
−1
−0.5
0 −1.5
−0.5
+0.5
dB Maximum Output Offset Voltage4 VG = −625 mV to +625 mV 5
30
10
45
mV Output Offset Variation VG = −625 mV to +625 mV 5
30
10
45
mV GAIN CONTROL INTERFACE Gain Scaling Factor +3 dB to +37 dB (AD600);
31.7
32
32.3 30.5
32
33.5
dB/V −7 dB to +27 dB (AD602) Common-Mode Range −0.75 +2.5 −0.75 +2.5 V Input Bias Current 0.35 1 0.35 1 μA Input Offset Current 10 50 10 50 nA Differential Input Resistance Pin 1 to Pin 16; Pin 8 to Pin 9 15 15 MΩ Response Rate Full 40 dB gain change 40 40 dB/μs Rev. F | Page 3 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION NOISE PERFORMANCE GAIN-CONTROL INTERFACE SIGNAL-GATING INPUTS COMMON-MODE REJECTION ACHIEVING 80 dB GAIN RANGE SEQUENTIAL MODE (MAXIMUM SNR) PARALLEL MODE (SIMPLEST GAIN-CONTROL INTERFACE) LOW RIPPLE MODE (MINIMUM GAIN ERROR) APPLICATIONS INFORMATION TIME-GAIN CONTROL (TGC) AND TIME-VARIABLE GAIN (TVG) INCREASING OUTPUT DRIVE DRIVING CAPACITIVE LOADS REALIZING OTHER GAIN RANGES ULTRALOW NOISE VCA LOW NOISE, 6 dB PREAMPLIFIER LOW NOISE AGC AMPLIFIER WITH 80 dB GAIN RANGE WIDE RANGE, RMS-LINEAR dB MEASUREMENT SYSTEM (2 MHz AGC AMPLIFIER WITH RMS DETECTOR) 100 dB TO 120 dB RMS RESPONDING CONSTANT BANDWIDTH AGC SYSTEMS WITH HIGH ACCURACY DECIBEL OUTPUTS 100 dB RMS/AGC SYSTEM WITH MINIMAL GAIN ERROR (PARALLEL GAIN WITH OFFSET) 120 dB RMS/AGC SYSTEM WITH OPTIMAL SNR (SEQUENTIAL GAIN) OUTLINE DIMENSIONS ORDERING GUIDE