Datasheet AD9279 (Analog Devices) - 9

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AD9279 ABSOLUTE MAXIMUM RATINGS Table 4.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any AVDD1 to GND −0.3 V to +2.0 V other conditions above those indicated in the operational AVDD2 to GND −0.3 V to +3.9 V section of this specification is not implied. Exposure to absolute DRVDD to GND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect GND to GND −0.3 V to +0.3 V device reliability. AVDD2 to AVDD1 −2.0 V to +3.9 V AVDD1 to DRVDD −2.0 V to +2.0 V
THERMAL IMPEDANCE
AVDD2 to DRVDD −2.0 V to +3.9 V Digital Outputs (DOUTx+, DOUTx−, −0.3 V to
Table 5.
DCO+, DCO−, FCO+, FCO−) to GND DRVDD + 0.3 V
Symbol Description Value1 Units
CLK+, CLK−, SDIO to GND −0.3 V to θJA Junction-to-ambient thermal 22.0 °C/W AVDD1 + 0.3 V resistance, 0.0 m/s air flow per LI-x, LO-x, LOSW-x to GND −0.3 V to JEDEC JESD51-2 (still air) AVDD2 + 0.3 V ΨJB Junction-to-board thermal 9.2 °C/W characterization parameter, 0 m/s CWI−, CWI+, CWQ−, CWQ+ to GND −0.3 V to air flow per JEDEC JESD51-8 (still air) AVDD2 + 0.3 V Ψ 0.12 °C/W PDWN, STBY, SCLK, CSB to GND −0.3 V to JT Junction-to-top-of-package characterization parameter, 0 m/s AVDD1 + 0.3 V air flow per JEDEC JESD51-2 (still air) GAIN+, GAIN−, RESET, 4LO+, 4LO−, −0.3 V to GPO0, GPO1, GPO2, GPO3 to GND AVDD2 + 0.3 V 1 Results are from simulations. PCB is JEDEC multilayer. Thermal performance for actual applications requires careful inspection of the conditions in the VREF to GND −0.3 V to application to determine if they are similar to those assumed in these AVDD1 + 0.3 V calculations. Operating Temperature Range (Ambient) −40°C to +85°C
ESD CAUTION
Storage Temperature Range (Ambient) −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Rev. 0 | Page 9 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE