AD9670Data SheetParameter1Test Conditions/CommentsMinTypMaxUnit Two-Tone Intermodulation fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz, −58 dB Distortion (IMD3) ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2 LO Harmonic Rejection 16LO, 8LO, and 4LO modes −20 dBc Quadrature Phase Error I to Q, all phases, 1 σ 0.15 Degrees I/Q Amplitude Imbalance I to Q, all phases, 1 σ 0.015 dB Channel-to-Channel Matching Phase I to I, Q to Q, 1 σ 0.5 Degrees Amplitude I to I, Q to Q, 1 σ 0.25 dB POWER SUPPLY, MODE I/MODE II/ MODE III/MODE IV AVDD1 1.7 1.8 1.9 V AVDD2 2.85 3.0 3.6 V DVDD Demodulator/decimator enabled 1.3 1.4 1.9 V Demodulator/decimator disabled 1.3 1.8 1.9 V DRVDD 1.7 1.8 1.9 V IAVDD1 TGC mode, LO band mode 148/187/ mA 223/291 CW Doppler mode 4 mA IAVDD2 TGC mode, no signal, low band mode 230 mA TGC mode, no signal, high band mode 239 mA CW Doppler mode, 8 channels enabled 140 mA IDVDD RF decimator enabled in Mode III and Mode IV; 156/247/ mA demodulator/decimator enabled all modes 166/255 IDRVDD ANSI-644 mode 133/184/ mA 141/146 Low power (IEEE 1596.3 similar) mode, 1 channel per 119/170/ mA lane mode 127/169 Total Power Dissipation TGC mode, no signal, RF decimator enabled in Mode III 1200/1400/ 1345/1555/ mW (Including Output Drivers) and Mode IV, demodulator/decimator disabled 1380/1630 1535/2100 TGC mode, no signal, RF decimator enabled in Mode III 1400/1695/ 1560/1880/ mW and Mode IV, demodulator/decimator enabled 1570/1900 1740/2100 CW Doppler mode, 8 channels enabled 500 mW Power-Down Dissipation 30 mW Standby Power Dissipation 630 mW ADC RESOLUTION 14 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±50 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 7.5 kΩ 1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 The overrange condition is specified as 6 dB more than the full-scale input range. 3 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be 4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly. Rev. A | Page 6 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE