Datasheet AD9675 (Analog Devices)

Octal Ultrasound AFE with JESD204B Data Sheet AD9675 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
The AD9675 is designed for low cost, low power, small size, and
Low power
ease of use for medical ultrasound. It contains eight channels of
150 mW per channel, TGC mode, 40 MSPS
a variable gain amplifier (VGA) with a low noise preamplifier
62.5 mW per channel, CW mode
(LNA), a continuous wave (CW) harmonic rejection I/Q
10 mm × 10 mm, 144-ball CSP_BGA
demodulator with programmable phase rotation, an antialiasing
TGC channel input referred noise: 0.82 nV/√Hz,
filter (AAF), an analog-to-digital converter (ADC), and a digital
maximum gain
high-pass filter and RF decimation by 2 for data processing and
Flexible power-down modes
bandwidth reduction.
Fast recovery from low power standby mode: 2 μs
Each channel features a maximum gain of up to 52 dB, a fully
Low noise preamplifier (LNA)
differential signal path, and an active input preamplifier termina-
Input referred noise: 0.78 nV/√Hz, gain = 21.6 dB
tion. The channel is optimized for high dynamic performance
Programmable gain: 15.6 dB, 17.9 dB, or 21.6 dB
and low power in applications where a small package size is critical.
0.1 dB compression: 1000 mV p-p, 750 mV p-p, or 450 mV p-p Flexible active input impedance matching
The LNA has a single-ended to differential gain that is selectable
Variable gain amplifier (VGA)
through the serial port interface (SPI). Assuming a 15 MHz
Attenuator range: 45 dB, linear in dB gain control
noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA
Postamp gain (PGA): 21 dB, 24 dB, 27 dB, or 30 dB
input SNR is 94 dB. In CW Doppler mode, each LNA output
Antialiasing filter (AAF)
drives an I/Q demodulator that has independently
Programmable second-order low-pass filter (LPF) from
programmable phase rotation with 16 phase settings.
8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass
Power-down of individual channels is supported to increase
filter (HPF)
battery life for portable applications. Standby mode allows quick
Analog-to-digital converter (ADC)
power-up for power cycling. In CW Doppler operation, the
SNR: 75 dB, 14 bits up to 125 MSPS
VGA, AAF, and ADC are powered down. The ADC contains
JESD204B Subclass 0 coded serial digital outputs
features to maximize flexibility and minimize system cost, such
CW Doppler mode harmonic rejection I/Q demodulator
as a programmable clock, data alignment, and programmable
Individual programmable phase rotation
digital test pattern generation. The digital test patterns include
Dynamic range per channel: 160 dBFS/√Hz
built-in fixed patterns, built-in pseudorandom patterns, and
Close-in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input
custom user-defined test patterns entered via the SPI.
RF digital decimation by 2 and high-pass filter APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide