Datasheet AD9690 (Analog Devices) - 2

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AD9690 Data Sheet TABLE OF CONTENTS
Features .. 1 DDC NCO Plus Mixer Loss and SFDR ... 42 Applications ... 1 Numerically Controlled Oscillator .. 42 Functional Block Diagram .. 1 FIR Filters .. 44 Product Highlights ... 1 General Description ... 44 Revision History ... 3 Half-Band Filters .. 45 General Description ... 4 DDC Gain Stage ... 47 Specifications ... 5 DDC Complex—Real Conversion ... 47 DC Specifications ... 5 DDC Example Configurations ... 48 AC Specifications .. 6 Digital Outputs ... 49 Digital Specifications ... 7 Introduction to the JESD204B Interface ... 49 Switching Specifications .. 8 JESD204B Overview .. 49 Timing Specifications .. 9 Functional Overview ... 50 Absolute Maximum Ratings .. 11 JESD204B Link Establishment ... 50 Thermal Characteristics .. 11 Physical Layer (Driver) Outputs .. 52 ESD Caution .. 11 JESD204B Tx Converter Mapping ... 54 Pin Configuration and Function Descriptions ... 12 Configuring the JESD204B Link .. 55 Typical Performance Characteristics ... 14 Multichip Synchronization .. 57 AD9690-1000 .. 14 SYSREF± Setup/Hold Window Monitor ... 59 AD9690-500 .. 18 Test Modes ... 61 Equivalent Circuits ... 22 ADC Test Modes .. 61 Theory of Operation .. 24 JESD204B Block Test Modes .. 62 ADC Architecture .. 24 Serial Port Interface .. 64 Analog Input Considerations .. 24 Configuration Using the SPI ... 64 Voltage Reference ... 28 Hardware Interface ... 64 Clock Input Considerations .. 29 SPI Accessible Features .. 64 ADC Overrange and Fast Detect .. 31 Memory Map .. 65 ADC Overrange .. 31 Reading the Memory Map Register Table ... 65 Fast Threshold Detection (FD) ... 31 Memory Map Register Table ... 66 Signal Monitor .. 32 Applications Information .. 77 SPORT Over JESD204B ... 32 Power Supply Recommendations ... 77 Digital Downconverter (DDC) ... 35 Exposed Pad Thermal Heat Slug Recommendations .. 77 DDC I/Q Input Selection .. 35 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .. 77 DDC I/Q Output Selection ... 35 Outline Dimensions ... 78 DDC General Description .. 35 Ordering Guide .. 78 Frequency Translation ... 41 General Description ... 41 Rev. B | Page 2 of 78 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9690-1000 AD9690-500 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing Voltage Reference Clock Input Considerations Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC Overrange and Fast Detect ADC Overrange Fast Threshold Detection (FD) Signal Monitor SPORT Over JESD204B Digital Downconverter (DDC) DDC I/Q Input Selection DDC I/Q Output Selection DDC General Description Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Plus Mixer Loss and SFDR Numerically Controlled Oscillator Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR Filters General Description Half-Band Filters HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC Gain Stage DDC Complex—Real Conversion DDC Example Configurations Digital Outputs Introduction to the JESD204B Interface JESD204B Overview Functional Overview Transport Layer Data Link Layer Physical Layer JESD204B Link Establishment Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder Physical Layer (Driver) Outputs Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B Tx Converter Mapping Configuring the JESD204B Link Multichip Synchronization SYSREF± Setup/Hold Window Monitor Test Modes ADC Test Modes JESD204B Block Test Modes Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes Serial Port Interface Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels SPI Soft Reset Memory Map Register Table Applications Information Power Supply Recommendations Exposed Pad Thermal Heat Slug Recommendations AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) Outline Dimensions Ordering Guide