Datasheet AD7466-KGD (Analog Devices) - 4

AD7466-KGD Known Good Die Parameter Min Typ Max Unit Test Conditions/Comments
CONVERSION RATE Conversion Time 4.70 µs 16 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 200 kSPS POWER REQUIREMENTS VDD 1.6 3.6 V IDD Digital inputs = 0 V or VDD Normal Mode (Operational) 300 µA VDD = 3 V, fSAMPLE = 100 kSPS 110 µA VDD = 3 V, fSAMPLE = 50 kSPS 20 µA VDD = 3 V, fSAMPLE = 10 kSPS 240 µA VDD = 2.5 V, fSAMPLE = 100 kSPS 80 µA VDD = 2.5 V, fSAMPLE = 50 kSPS 16 µA VDD = 2.5 V, fSAMPLE = 10 kSPS 165 µA VDD = 1.8 V, fSAMPLE = 100 kSPS 50 µA VDD = 1.8 V, fSAMPLE = 50 kSPS 10 µA VDD = 1.8 V, fSAMPLE = 10 kSPS Power-Down Mode 0.1 µA SCLK on or off, typically 8 nA Power Dissipation Normal Mode (Operational) 0.9 mW VDD = 3 V, fSAMPLE = 100 kSPS 0.6 mW VDD = 2.5 V, fSAMPLE = 100 kSPS 0.3 mW VDD = 1.8 V, fSAMPLE = 100 kSPS Power-Down Mode 0.3 µW VDD = 3 V Rev. A | Page 4 of 9 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE