Datasheet ADL5335 (Analog Devices) - 6

ADL5335 Data Sheet DIGITAL LOGIC TIMING Table 2. Parameter Description Min Typ Max Unit
tCLK Maximum serial clock rate 25 MHz tHI Minimum period that SCLK is in a logic high state 10 ns tLO Minimum period that SCLK is in a logic low state 10 ns tS Setup time between falling edge of CS and SCLK 15 ns tH Hold time between data and rising edge of SCLK 5 ns tDS Setup time between data and rising edge of SCLK 15 ns tDH SCLK to SDIO Hold Time 10 ns tZ Maximum time delay between CS deactivation and SDIO bus to return to high impedance 5 ns tACCESS Maximum time delay between falling edge of SCLK and out data valid for a read operation 5 ns
SPI Timing Diagram tDS tHI tCLK tH tS t t DH tLO ACCESS CS SCLK DON’T CARE DON’T CARE tZ SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE
-002 304 16 Figure 2. SPI Timing Rev. 0 | Page 6 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DIGITAL LOGIC TIMING SPI Timing Diagram ABSOLUTE MAXIMUM RATINGS THREMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE DIGITAL INTERFACE OVERVIEW Serial Peripheral Interface (SPI) Fast Attack (FA) APPLICATIONS INFORMATION BASIC CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE