Datasheet LTC2321-16 (Analog Devices) - 4

LTC2321-16
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 0.8 • OVDD V VIL Low Level Input Voltage l 0.2 • OVDD V IIN Digital Input Current VIN = 0V to OVDD l –10 10 μA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage IO = -500µA l OVDD – 0.2 V VOL Low Level Output Voltage IO = 500µA l 0.2 V IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = OVDD 10 mA VID LVDS Differential Input Voltage 100Ω Differential Termination OVDD = 2.5V l 240 600 mV VIS LVDS Common Mode Input Voltage 100Ω Differential Termination OVDD = 2.5V l 1 1.45 V VOD LVDS Differential Output Voltage 100Ω Differential Load, LVDS Mode l 100 150 300 mV OVDD = 2.5V VOS LVDS Common Mode Output Voltage 100Ω Differential Load, LVDS Mode l 0.85 1.2 1.4 V OVDD = 2.5V VOD_LP Low Power LVDS Differential Output 100Ω Differential Load, LVDS Mode l 75 100 250 mV Voltage OVDD = 2.5V VOS_LP Low Power LVDS Common Mode 100Ω Differential Load, LVDS Mode l 0.9 1.2 1.4 V Output Voltage OVDD = 2.5V
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation l 4.75 5.25 V 3.3V Operation l 3.13 3.47 V OVDD Supply Voltage l 1.71 2.63 V IVDD Supply Current 2Msps Sample Rate (IN+ = IN– = 0V) l 11.8 15 mA IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) CMOS Mode l 1.8 2 mA 2Msps Sample Rate (RL = 100Ω) LVDS Mode l 7.1 11 mA INAP Nap Mode Current Conversion Done (IVDD) l 2.55 5 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) CMOS Mode l 1 5 μA Sleep Mode (IVDD + IOVDD) LVDS Mode l 1 5 μA PD_3.3V Power Dissipation VDD = 3.3V 2Msps Sample Rate (IN+ = IN– = 0V) CMOS Mode l 37 58 mW VDD = 3.3V 2Msps Sample Rate (IN+ = IN– = 0V) LVDS Mode l 52 86 mW Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) CMOS Mode l 7.8 13 mW VDD = 3.3V Conversion Done (IVDD + IOVDD) LVDS Mode l 26 41 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) CMOS Mode l 5 16.5 μW VDD = 3.3V Sleep Mode (IVDD + IOVDD) LVDS Mode l 5 16.5 μW PD_5V Power Dissipation VDD = 5V 2Msps Sample Rate (IN+ = IN– = 0V) CMOS Mode l 62 80 mW VDD = 5V 2Msps Sample Rate (IN+ = IN– = 0V) LVDS Mode l 77 102.5 mW Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) CMOS Mode l 13 25 mW VDD = 5V Conversion Done (IVDD + IOVDD) LVDS Mode l 31 40 mW Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) CMOS Mode l 5 25 μW VDD = 5V Sleep Mode (IVDD + IOVDD) LVDS Mode l 5 25 μW Rev. D 4 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts