Datasheet AD5235-EP (Analog Devices) - 8

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AD5235-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK 1 16 RDY SDI 2 15 CS SDO 3 14 PR GND 4 AD5235-EP 13 WP TOP VIEW VSS 5 12 VDD (Not to Scale) A1 6 11 A2 W1 7 10 W2
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B1 8 9 B2
0 185- 09 Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. 2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first. 3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. 4 GND Ground Pin, Logic Ground Reference. 5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink 35 mA for 30 ms when storing data to EEMEM. 6 A1 Terminal A of RDAC1. 7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0. 8 B1 Terminal B of RDAC1. 9 B2 Terminal B of RDAC2. 10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1. 11 A2 Terminal A of RDAC2. 12 VDD Positive Power Supply. 13 WP Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe. CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Tie WP to VDD, if not used. 14 PR Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated at the logic high transition. Tie PR to VDD, if not used. 15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. 16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and PR. Rev. B | Page 8 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE