Datasheet LTM4632 (Analog Devices) - 7

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PIN FUNCTIONS VIN (A2, B3, D3, E2):
Power Input Pins. Apply input shuts down the specific regulator channel. Do not float voltage between these pins and GND pins. Recommend this pin. placing input decoupling capacitance directly between VIN
COMP1 (E5), COMP2 (A5):
Current Control Threshold and pins and GND pins. Error Amplifier Compensation Point of Each Switching
VOUT1 (D1, E1), VOUT2 (A1, B1):
Power Output Pins of Mode Regulator Channel. The current comparator’s trip each Switching Mode Regulator. Apply output load be- threshold is linearly proportional to this voltage, whose tween these pins and GND pins. Recommend placing out- normal range is from 0.3V to 1.8V. The device is inter- put decoupling capacitance directly between these pins nal compensated. Tie COMP pins together in Dual Phase and GND pins. Single Output VTT Configuration. See the Applications
GND (C1-C2, C4, B5, D5):
Power Ground Pins for Both Information section for details. Input and Output Returns.
FB1 (E4):
The Negative Input of the Error Amplifier for
PGOOD1 (D4):
Output Power Good with Open-Drain Logic the Channel 1 Switching Mode Regulator. Internally, of the Channel 1 Switching Mode Regulator. PGOOD1 is this pin is connected to VOUT1 with a 60.4k precision pulled to ground when the voltage on the FB1 pin is not resistor. Different output voltages can be programmed within ±8% (typical) of the internal 0.6V reference. This with an additional resistor between FB1 and GND pins. threshold has 15mV of hysteresis. Connect this pin to INTVCC in Dual Phase Single Output VTT Configuration. See the Applications Information sec-
PGOOD2 (B4):
Output Power Good with Open-Drain Logic tion for details. of the Channel 2 Switching Mode Regulator. PGOOD2 is pulled to ground when the voltage on the V
TRACK/SS1 (E3):
Output Tracking and Soft-Start Pin of OUT2 pin is not within ±8% (typical) of the V the Channel 1 Switching Mode Regulator. It al ows the DDQIN/2 voltage. This threshold has 15mV of hysteresis. user to control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses the internal
SYNC/MODE (C5):
Mode Select and External reference input to the error amplifier, instead it servos the Synchronization Input. Tie this pin to ground to force FB pin to the TRACK/SS voltage. Above 0.6V, the tracking continuous synchronous operation at all output loads. function stops and the internal reference resumes control Floating this pin or tying it to INTVCC enables high effi- of the error amplifier. There’s an internal 1.2µA pull-up ciency Burst Mode operation at light loads. Drive this current from INTVCC on this pin, so putting a capacitor pin with a clock to synchronize the LTM4632 switching here provides a soft-start function. frequency. An internal phase-locked loop will force the bottom power NMOS’s turn on signal to be synchronized
VTTR (A3):
Reference Output. This output is used to sup- with the rising edge of the clock signal. When this pin is ply the VREF voltage for DDR memory. An on-chip buffer driven with a clock, forced continuous mode is automati- amplifier outputs a low noise reference voltage equal to cally selected. VDDQIN/2. This output is capable of supplying 10mA. VTTR has internal 0.01µF capacitor. Additional R-C filter can
INTVCC (C3):
Internal 3.3V Regulator Output of the be used to further reduce the ripple on VTTR. The error Switching Mode Regulator Channel. The internal power amplifier for channel 2 uses this voltage as its reference drivers and control circuits are powered from this volt- voltage. age. This pin is internally decoupled to GND with a 2.2µF low ESR ceramic capacitor. No more external decoupling
VDDQIN (A4):
External Reference Input for Channel 2. An capacitor needed. internal resistor divider sets the VTTR pin voltage to be equal to half the voltage applied to this input. Channel 2
RUN1 (D2), RUN2 (B2):
Run Control Input of Each uses the VTTR pin voltage as its error amplifier reference. Switching Mode Regulator Channel. Enables chip opera- tion by tying RUN above 1.28V. Tying this pin below 1V Rev. D For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts