Datasheet ACS71020 (Allegro) - 8

Single Phase, Isolated, Power Monitoring IC ACS71020 with Voltage Zero Crossing and Overcurrent Detection xKMATR-SPI OPERATING CHARACTERISTICS:
Valid through the full range of TA, VCC = VCC(nom), unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit SPI INTERFACE CHARACTERISTICS
MOSI, SCLK, CS pins, V Digital Input High Voltage V CC (nom) = 3.3 V 2.8 – 3.63 V IH MOSI, SCLK, CS pins, VCC (nom) = 5 V 4 – 5.5 V Digital Input Low Voltage VIL MOSI, SCLK, CS pins – – 0.5 V MISO pin, CL = 20 pF, TA = 25°C, V SPI Output High Voltage V CC (nom) = 3.3 V 2.8 3.3 3.8 V OH MISO pin, CL = 20 pF, TA = 25°C, VCC (nom) = 5 V 4 5 5.5 V SPI Output Low Voltage VOL MISO pin, CL = 20 pF, TA = 25°C – 0.3 0.5 V SPI Clock Frequency fSCLK MISO pin, CL = 20 pF 0.1 – 10 MHz SPI Frame Rate tSPI 5.8 – 588 kHz Chip Select to First SCLK Edge t Time from CS going low to SCLK falling CS edge 50 – – ns Data Output Valid Time tDAV Data output valid after SCLK falling edge – 40 – ns MOSI Setup Time tSU Input setup time before SCLK rising edge 25 – – ns MOSI Hold Time tHD Input hold time after SCLK rising edge 50 – – ns SCLK to CS Hold Time t Hold SCLK high time before CS rising CHD edge 5 – – ns Load Capacitance CL Loading on digital output (MISO) pin – – 20 pF
Figure 3: SPI Timing
Allegro MicroSystems, LLC 8 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing