Datasheet ADSP-BF561 (Analog Devices) - 6

link to page 6 ADSP-BF561 flexible configuration and upgradability of system memory • Interrupts – Events that occur asynchronously to program while allowing the core to view all SDRAM as a single, contigu­ flow. They are caused by timers, peripherals, input pins, ous, physical address space. and an explicit software instruction. The asynchronous memory controller can also be programmed Each event has an associated register to hold the return address to control up to four banks of devices with very flexible timing and an associated “return from event” instruction. When an parameters for a wide variety of devices. Each bank occupies a event is triggered, the state of the processor is saved on the 64M byte segment regardless of the size of the devices used so supervisor stack. that these banks will only be contiguous if fully populated with The ADSP-BF561 event controller consists of two stages: the 64M bytes of memory. Core Event Controller (CEC) and the System Interrupt Control­
I/O Memory Space
ler (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Blackfin processors do not define a separate I/O space. All Conceptually, interrupts from the peripherals enter into the resources are mapped through the flat 32-bit address space. On- SIC, and are then routed directly into the general-purpose chip I/O devices have their control registers mapped into mem­ interrupts of the CEC. ory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller
Core Event Controller (CEC)
blocks, one which contains the control MMRs for all core func­ The CEC supports nine general-purpose interrupts (IVG15–7), tions, and the other which contains the registers needed for in addition to the dedicated interrupt and exception events. Of setup and control of the on-chip peripherals outside of the core. these general-purpose interrupts, the two lowest priority inter­ The core MMRs are accessible only by the core and only in rupts (IVG15–14) are recommended to be reserved for software supervisor mode and appear as reserved space by on-chip interrupt handlers, leaving seven prioritized interrupt inputs to peripherals. The system MMRs are accessible by the core in support the peripherals of the ADSP-BF561. Table 1 describes supervisor mode and can be mapped as either visible or reserved the inputs to the CEC, identifies their names in the Event Vector to other devices, depending on the system protection Table (EVT), and lists their priorities. model desired.
Booting Table 1. Core Event Controller (CEC)
The ADSP-BF561 contains a small boot kernel, which config­
Priority
ures the appropriate peripheral for booting. If the ADSP-BF561
(0 is Highest) Event Class EVT Entry
is configured to boot from boot ROM memory space, the pro­ 0 Emulation/Test Control EMU cessor starts executing from the on-chip boot ROM. 1 Reset RST
Event Handling
2 Nonmaskable Interrupt NMI 3 Exceptions EVX The event controller on the ADSP-BF561 handles all asynchro­ nous and synchronous events to the processor. The 4 Global Enable ADSP-BF561 provides event handling that supports both nest­ 5 Hardware Error IVHW ing and prioritization. Nesting allows multiple event service 6 Core Timer IVTMR routines to be active simultaneously. Prioritization ensures that 7 General Interrupt 7 IVG7 servicing of a higher priority event takes precedence over servic­ 8 General Interrupt 8 IVG8 ing of a lower priority event. The controller provides support for five different types of events: 9 General Interrupt 9 IVG9 • Emulation – An emulation event causes the processor to 10 General Interrupt 10 IVG10 enter emulation mode, allowing command and control of 11 General Interrupt 11 IVG11 the processor via the JTAG interface. 12 General Interrupt 12 IVG12 • Reset – This event resets the processor. 13 General Interrupt 13 IVG13 • Nonmaskable Interrupt (NMI) – The NMI event can be 14 General Interrupt 14 IVG14 generated by the software watchdog timer or by the NMI 15 General Interrupt 15 IVG15 input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut­
System Interrupt Controller (SIC)
down of the system. The System Interrupt Controller provides the mapping and • Exceptions – Events that occur synchronously to program routing of events from the many peripheral interrupt sources to flow, i.e., the exception will be taken before the instruction the prioritized general-purpose interrupt inputs of the CEC. is allowed to complete. Conditions such as data alignment Although the ADSP-BF561 provides a default mapping, the user violations or undefined instructions cause exceptions. can alter the mappings and priorities of interrupt events by Rev. E | Page 6 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide