Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 63

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ADSP-BF534/ADSP-BF536/ADSP-BF537 OUTLINE DIMENSIONS
Dimensions in Figure 67 and Figure 68 are shown in millimeters.
A1 CORNER 12.00 BSC SQ INDEX AREA 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B PIN A1 C INDICATOR D LOCATION E 10.40 F BSC G SQ H 0.80 J BSC K TYP L M N P TOP VIEW BOTTOM VIEW DETAIL A 1.31 1.70 MAX 1.21 1.10 0.25 MIN 0.50 SEATING 0.12 0.45 PLANE COPLANARITY NOTES: 0.40 1. COMPLIANT TO JEDEC STANDARD MO-205-AE, (BALL EXCEPT FOR BALL DIAMETER. DIAMETER) 2. CENTER DIMENSIONS ARE NOMINAL. DETAIL A 3. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES
Figure 67. 182-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-182) Dimensions shown in millimeters Rev. J | Page 63 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide