Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 5

ADSP-BF542 /ADSP-BF544 /ADSP-BF547/ ADSP-BF548 /ADSP-BF549
length, and base registers (for circular buffering), and eight The architecture provides three modes of operation: user mode, additional 32-bit pointer registers (for C-style indexed stack supervisor mode, and emulation mode. User mode has manipulation). restricted access to certain system resources, thus providing a Blackfin processors support a modified Harvard architecture in protected software environment, while supervisor mode has combination with a hierarchical memory structure. Level 1 (L1) unrestricted access to the system and core resources. memories are those that typically operate at the full processor The Blackfin processor instruction set has been optimized so speed with little or no latency. At the L1 level, the instruction that 16-bit opcodes represent the most frequently used instruc- memory holds instructions only. The two data memories hold tions, resulting in excellent compiled code density. Complex data, and a dedicated scratchpad data memory stores stack and DSP instructions are encoded into 32-bit opcodes, representing local variable information. fully featured multifunction instructions. Blackfin processors In addition, multiple L1 memory blocks are provided, offering a support a limited multi-issue capability, where a 32-bit instruc- configurable mix of SRAM and cache. The memory manage- tion can be issued in parallel with two 16-bit instructions, ment unit (MMU) provides memory protection for individual allowing the programmer to use many of the core resources in a tasks that may be operating on the core and can protect system single instruction cycle. registers from unintended access. The Blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 DAG0 P3 P2 DA1 32 P1 DA0 32 P0 32 32 RAB PREG TO MEMORY SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER A0 40 40 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core Rev. E | Page 5 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide