LTC3827-1 FUNCTIONAL DIAGRAM PLLIN/MODE INTVCC VIN DUPLICATE FOR SECOND FIN 6 PHASE DET CONTROLLER CHANNEL DB 100k BOOST 24, 17 PLLLPF TG CB 5 CLK1 DROP TOP RLP OUT CIN OSCILLATOR 26, 15 D CLK2 DET BOT FC SW CLP – 0.88V TOP ON S Q + SWITCH 25, 16 INTVCC V R Q FB1 LOGIC PGOOD1 BG – BOT 27 + 0.72V 23, 18 BURSTEN C PGND OUT B 0.4V + SLEEP 21 VOUT – SHDN RSENSE INTV L CC-0.5V – FC + ICMP IR + – PLLIN/MODE – – + + – BURSTEN – + 0.8V + SENSE+ 6mV 0.45V 3, 11 2(VFB) SENSE– 4, 10 SLOPE COMP VFB RB VFB – EA TRACK/SS 2, 12 + 0.80V RA VIN OV + VIN 22 – 0.88V 4.7V + CC I 5.25V/ 0.5μA TH EXTV – CC 7.5V 1,13 LDO SHDN 20 C R RST FOLDBACK C2 C 6V INTV 1μA CC 2(VFB) + 19 TRACK/SS RUN SGND INTERNAL 8, 9 28,14 SUPPLY 7 SHDN CSS 38271 FD OPERATION (Refer to Functional Diagram) Main Control Loop the VFB pin, (which is generated with an external resis- tor divider connected across the output voltage, V The LTC3827-1 uses a constant frequency, current mode OUT, to ground) to the internal 0.800V reference voltage. When the step-down architecture with the two controller channels load current increases, it causes a slight decrease in V operating 180 degrees out of phase. During normal op- FB relative to the reference, which causes the EA to increase eration, each external top MOSFET is turned on when the the I clock for that channel sets the RS latch, and is turned off TH voltage until the average inductor current matches the new load current. when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and After the top MOSFET is turned off each cycle, the bottom resets the latch is controlled by the voltage on the ITH pin, MOSFET is turned on until either the inductor current starts which is the output of the error amplifi er EA. The error to reverse, as indicated by the current comparator IR, or amplifi er compares the output voltage feedback signal at the beginning of the next clock cycle. 38271fe 9
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