Datasheet LTC3405A-1.375 (Analog Devices) - 9

LTC3405A-1.375
U U W U APPLICATIO S I FOR ATIO Efficiency Considerations
the DC bias current. In continuous mode, IGATECHG = The efficiency of a switching regulator is equal to the f(QT + QB) where QT and QB are the gate charges of the output power divided by the input power times 100%. It is internal top and bottom switches. Both the DC bias and often useful to analyze individual losses to determine what gate charge losses are proportional to VIN and thus is limiting the efficiency and which change would produce their effects will be more pronounced at higher supply the most improvement. Efficiency can be expressed as: voltages. Efficiency = 100% – (L1 + L2 + L3 + ...) 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In where L1, L2, etc. are the individual losses as a percentage continuous mode, the average output current flowing of input power. through inductor L is “chopped” between the main Although all dissipative elements in the circuit produce switch and the synchronous switch. Thus, the series losses, two main sources usually account for most of the resistance looking into the SW pin is a function of both losses in LTC3405A-1.375 circuits: V top and bottom MOSFET R IN quiescent current DS(ON) and the duty cycle and I2R losses. The V (DC) as follows: IN quiescent current loss dominates the efficiency loss at very low load currents whereas the RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency The RDS(ON) for both the top and bottom MOSFETs can curve at very low load currents can be misleading since the be obtained from the Typical Performance Charateristics actual power lost is of no consequence as illustrated in curves. Thus, to obtain I2R losses, simply add RSW to Figure 2. RL and multiply the result by the square of the average output current. 1 VIN = 3.6V Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less 0.1 than 2% total additional loss. 0.01
Thermal Considerations
In most applications, the LTC3405A-1.375 does not POWER LOST (W) 0.001 dissipate much heat due to its high efficiency. But, in applications where they run at high ambient temperature with low supply voltage, the heat dissipated may exceed 0.0001 0.1 1 10 100 1000 the maximum junction temperature of the part. If the LOAD CURRENT (mA) junction temperature reaches approximately 150°C, both 3405A1375 F02 power switches will be turned off and the SW node will
Figure 2. Power Lost vs Load Current
become high impedance. 1. The VIN quiescent current is due to two components: To keep the LTC3405A-1.375 from exceeding the maxi- the DC bias current as given in the electrical character- mum junction temperature, the user will need to do some istics and the internal main switch and synchronous thermal analysis. The goal of the thermal analysis is to switch gate charge currents. The gate charge current determine whether the power dissipated exceeds the results from switching the gate capacitance of the maximum junction temperature of the part. The tempera- internal power MOSFET switches. Each time the gate is ture rise is given by: switched from high to low to high again, a packet of TR = (PD)(θJA) charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than 3405a1375f 9