Datasheet LTC3447 (Analog Devices) - 8

LTC3447
U OPERATIO
the user should calculate the power dissipation when for duty cycles >40%; however, the LTC3447 uses a the LTC3447 is used at 100% duty cycle with low input patent-pending scheme that counteracts this compensat- voltage (See Thermal Considerations in the Applications ing ramp, which allows the maximum inductor peak current Information section). to remain unaffected throughout all duty cycles.
Low Supply Operation DAC
The LTC3447 will operate with input supply voltages as The I2C interface is used to control the internal voltage low as 2.5V, but the maximum allowable output current DAC for the buck regulator. The output voltage range is is reduced at this low voltage. Figure 4 shows the reduc- 0.69V to 2.05V in 21.6mV steps. The default DAC setting tion in the maximum output current as a function of input is 100000 which equates to a 1.38V output voltage. Output voltage for various output voltages. voltage transitions begin once the I2C interface receives the STOP command.
Slope Compensation and Inductor Peak Current Slew Rate
Slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscil- The LTC3447 has a slew rate of approximately 11mV/µs. lations at high duty cycles. It is accomplished internally The slew rate is controlled by the RC time constant of a by adding a compensating ramp to the inductor current low pass fi lter at the voltage DAC output. Figure 5 shows signal at duty cycles in excess of 40%. Normally, this a typical transition from min to max DAC settings. results in a reduction of maximum inductor peak current 1200 TA = 25°C BURST MODE OPERATION DAC = MIN VIN = 3.6V 1100 VOUT 500mV/DIV 1000 DAC = MAX INDUCTOR CURRENT 900 200mA/DIV 800 MAXIMUM LOAD CURRENT (mA) 5V/DIV PGOOD 700 2.5 3.0 3.5 4.0 4.5 5.0 5.5 100µs/DIV SUPPLY VOLTAGE (V) 3447 F04
Figure 4. Maximum Load Current vs Supply Voltage Figure 5.Transition from DAC = MIN to DAC = MAX
SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 S P START ADDRESS R/W ACK DATA ACK DATA ACK ST0P COMMAND COMMAND 3447 TD02
Figure 6. Typical I2C Write Protocol
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