Datasheet AD8372 (Analog Devices) - 9

Data Sheet AD8372 50 45 A 40 V = 0dB 35 B) d ( 30 AV = 10dB E UR 25 IG F AV = 20dB E 20 IS NO 15 10 AV = 32dB
1
5
01 1- 05
0
07
20 40 60 80 100 120 140 160 180 200
2
0 20ns/DIV
-01 051
FREQUENCY (MHz)
07 Figure 11. Noise Figure vs. Frequency Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge
0 –10 –20 –30 –40 ) B (d –50 –60 –70 –80 –90
3
1M 10M 100M 1G
01 1- 05
FREQUENCY (Hz)
07 Figure 12. Isolation, Input to Opposite Output at Maximum Gain (To calculate output to output gain, subtract 29 dB from this plot) Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS SERIAL CONTROL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SINGLE-ENDED AND DIFFERENTIAL SIGNALS PASSIVE FILTER TECHNIQUES DIGITAL GAIN CONTROL DRIVING ANALOG-TO-DIGITAL CONVERTERS EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE