Datasheet LTC4101 (Analog Devices) - 9

LTC4101
BLOCK DIAGRAM
C4 R4 VBAT 0.03μF 3k 100Ω BAT V – SET VBAT 18 22 + 11.67μA C5, 0.1μF 11-BIT RSENSE V 20μF GND DAC – 12 CA1 3k CSP DCIN + 21 1.28V 0V OSCILLATOR CSP 9k WATCHDOG Ω DETECT t BUFFERED SYSTEM ON gm = 1m – ITH LOAD 20μF EA ÷5 + 1.19V CLP + – L1 TGATE S CSP Q2 1 Q ICMP R PWM I – REV 17mV LOGIC I D1 BGATE + DC Q3 3 20 R1 PGND C8 – 2 0.068μF 100mV Ω CA2 CLN gm = 1.5m Ω + 23 + C9 gm = 1m 1.19V R I CL TH CLP CL1 19 24 – 10-BIT R5, 6.04k C7 DCIN 5 I 0.0015μF DAC C6, 0.12μF 5.8V INFET 10 ACP Q1 4 CLP DCDIV 11 VIN VIN CHGEN 6 R10 V R11 DD 1.2V C1, 0.1μF 10μA SMBALERT 7 17 VDD TO SMBUS POWER SUPPLY SMBus TO HOST AND BATTERY INTERFACE SDA 8 AND CONTROL ILIM 13 LIMIT SCL 9 1.13k DECODER VLIM 14 16 THERMISTER THA INTERFACE 15 RVLIM RILIM THB 54.9k 10k
Figure 2.
4101fa 9